Browse Prior Art Database

Reset Controls for Asynchronous Operations in a Storage Hierarchy

IP.com Disclosure Number: IPCOM000041410D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Leung, PL: AUTHOR [+2]

Abstract

Storage hierarchies conduct data transfer operations between various levels of the hierarchy in an asynchronous and somewhat independent manner of using a host processor. A host processor can send a reset to the hierarchy at any time, independent of such data transfer operations. For ensuring data integrity, in recovering from a reset, a storage hierarchy will interrupt the asynchronous operations, maintain allegiance of the lower level hierarchical storage devices to the upper levels, prime a response of a lower level to the upper level and then proceed with the reset. Upon completion of the reset, the primed lower level will interrupt the upper level such that the interrupted asynchronous data processing operation can ensue for ensuring data integrity.

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Reset Controls for Asynchronous Operations in a Storage Hierarchy

Storage hierarchies conduct data transfer operations between various levels of the hierarchy in an asynchronous and somewhat independent manner of using a host processor. A host processor can send a reset to the hierarchy at any time, independent of such data transfer operations. For ensuring data integrity, in recovering from a reset, a storage hierarchy will interrupt the asynchronous operations, maintain allegiance of the lower level hierarchical storage devices to the upper levels, prime a response of a lower level to the upper level and then proceed with the reset. Upon completion of the reset, the primed lower level will interrupt the upper level such that the interrupted asynchronous data processing operation can ensue for ensuring data integrity. One or more host processors are connected to a plurality of control units to a buffer. The buffer constitutes an upper level of the two-level storage hierarchy. The buffer can be managed as a caching buffer. The lower level of the storage hierarchy can be a DASD (direct- access storage device) or any other retentive type of data storage unit. Typically, the control units will be coupled to the DASD through a storage controller with access to the DASD being handled through an electronic switch diagrammatically shown as a single-pole, single-throw switch. The storage controller has a plurality of storage bits for indicating to the control unit device status. Included in such status bits is a prime for a device end (DE). DE prime indicates to the storage controller that at the first opportunity a device end interruption signal should be supplied to the control unit to which the device owes allegiance as indicated by the status of the device switch. When a control unit receives a reset signal from a host processor, it has re...