Browse Prior Art Database

On-Wafer and On-Module Chip Testing

IP.com Disclosure Number: IPCOM000041423D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 8 page(s) / 80K

Publishing Venue

IBM

Related People

Tsui, F: AUTHOR

Abstract

Schemes are known in the prior art for testing logic chips, one of which is described in U.S. Patent 4,244,048. Some of these techniques allow LSI-logic chips to be tested extensively on-wafer and later, also, on-module. These schemes involve the utilization of the latches already provided on a chip, the utilization of the serial-shift arrangement (LSSD-like) provided on the chip, the incorporation of gating in the serial-shift outputs, and the addition of supplementary latches, if necessary. Incorporation of prepared connections for joining chips in an array on the wafer was also used, as well as a chip layout design and connection of probe-contact pads to the circuit array on the wafer to allow on-wafer chip testing, and the connection of chips on a module to allow on-module chip testing.

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On-Wafer and On-Module Chip Testing

Schemes are known in the prior art for testing logic chips, one of which is described in U.S. Patent 4,244,048. Some of these techniques allow LSI-logic chips to be tested extensively on-wafer and later, also, on-module. These schemes involve the utilization of the latches already provided on a chip, the utilization of the serial-shift arrangement (LSSD-like) provided on the chip, the incorporation of gating in the serial-shift outputs, and the addition of supplementary latches, if necessary. Incorporation of prepared connections for joining chips in an array on the wafer was also used, as well as a chip layout design and connection of probe-contact pads to the circuit array on the wafer to allow on-wafer chip testing, and the connection of chips on a module to allow on-module chip testing. Sometimes the provision of supplementary latches can be very expensive and for this reason the present article proposes to use subgrouping on-chip functions to be tested, and a combination of supplies to CN (combinatorial network) and control-inputs. Additionally, latches are grouped as much as possible to be set in the test-mode. Feedback from the output to the input allows testing, and gating is incorporated in the feedback circuits to eliminate the need for many of the supplementary latches. Provision of Serial-Shift Arrangements on the Chips The serial-shift arrangement (SSA) is a scheme for furnishing a means for transferring data into and out of a chip for testing purposes under the constraints of I/O limitation. Essentially, the SSA consists in connecting all the latches on a chip into one or more shiftable chains and utilizing these in a "scan-mode" of operation under appropriate controls. In this scan-mode (SM), contents, as needed, will be shifted into the latches. Then, in a test-mode (TM), the logic circuits will be allowed to run through one or more timing cycles, at the end of which the logic-circuit outputs will be fed into the latches. Finally, in the scan-mode again, contents of the latches (the test results) will be shifted out for inspection. By proper design of the interconnections of the chips on the modules and in a system, the SSA can be used also for testing on the module and system levels. Thus, the SSA can make LSI/VLSI logic testable at the cost of using only a small number of I/Os (chip-pads, module-pins, etc.) and a moderate amount of additional circuitry. The chip design should include the SSA feature: All latches on the chip should be connected to form one or more chains, to be shiftable in the scan-mode under appropriate controls. Provision of Single-Cycle and Multiple-Cycle Test-Mode Run Controls on the Chips This is a basic requirement to facilitate the chip testing, since the transfer (input and output) of test data into and out of the chips using the SSA mentioned above can be done only in the scan-mode and only when the circuitry under test is halted
(i.e., not running in...