Browse Prior Art Database

Epi-Overlayer Self-Aligned MESFET

IP.com Disclosure Number: IPCOM000041425D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Solomon, PM: AUTHOR

Abstract

This article relates generally to gallium arsenide MESFETs (Metal Semiconductor Field-Effect Transistors) and more particularly to structures which reduce the source-gate resistance due to surface states in such devices. Implementation of normally-off GaAs MESFETs is difficult because of the phenomenon of surface depletion whereby the surface of the GaAs between the drain and gate or source and gate regions is partially depleted, resulting in high parasitic resistance. Ways of overcoming this problem have been through the use of a recessed gate structure, or by using the gate as a mask to implant these regions in a similar manner to the source-drain implants of a polysilicon gate MOSFET [*]. A disadvantage of this prior-art method is that the gate has to withstand the temperature of the ion-implant anneal (>800ŒC).

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Epi-Overlayer Self-Aligned MESFET

This article relates generally to gallium arsenide MESFETs (Metal Semiconductor Field-Effect Transistors) and more particularly to structures which reduce the source-gate resistance due to surface states in such devices. Implementation of normally-off GaAs MESFETs is difficult because of the phenomenon of surface depletion whereby the surface of the GaAs between the drain and gate or source and gate regions is partially depleted, resulting in high parasitic resistance. Ways of overcoming this problem have been through the use of a recessed gate structure, or by using the gate as a mask to implant these regions in a similar manner to the source-drain implants of a polysilicon gate MOSFET [*]. A disadvantage of this prior-art method is that the gate has to withstand the temperature of the ion-implant anneal (>800OEC). Also, the large impurity concentrations used reduce breakdown voltages and nobilities in this region. The above figure shows a MESFET and current-limiting resistor consisting of an epitaxial n-GaAs overlayer deposited on an n-GaAs active layer and over a metal gate to accommodate the surface depletion. The epi-layer is more lightly doped than the active layer and is fully depleted over the metal gate region. Advantages of this scheme are as follows: 1. The epi-layer can be put down by Molecular Beam Epitaxy (MBE) or Metal Organic Chemical Vapor Deposition

(MOCVD) at temperatures >600 C. 2. The ungated regions have wel...