Browse Prior Art Database

Clocked Power Supply to Protect Against Latch-Up in CMOS Circuits

IP.com Disclosure Number: IPCOM000041426D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Gheewala, TR: AUTHOR

Abstract

Latch-up in CMOS (Complementary Metal Oxide Semiconductor) is a major problem which can cause serious damage to CMOS chips. Several improvements to the CMOS fabrication process have been suggested to improve the latch-up behavior of CMOS circuits. These include the use of epitaxial layers and deep, isolation trenches, which would add considerable cost and delay to the development of a usable CMOS process. A clocked power supply scheme is proposed here which, instead of eliminating the latch-up problem at great cost, allows the systems to live with the problem. It also permits the use of higher supply voltages, resulting in correspondingly higher performance. The proposed scheme is illustrated in the figure. Typical values for T1 and T2 would be T1 = 50 ms T2 = 100 ms. resulting in only 0.05% reduction in system availability.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 72% of the total text.

Page 1 of 2

Clocked Power Supply to Protect Against Latch-Up in CMOS Circuits

Latch-up in CMOS (Complementary Metal Oxide Semiconductor) is a major problem which can cause serious damage to CMOS chips. Several improvements to the CMOS fabrication process have been suggested to improve the latch-up behavior of CMOS circuits. These include the use of epitaxial layers and deep, isolation trenches, which would add considerable cost and delay to the development of a usable CMOS process. A clocked power supply scheme is proposed here which, instead of eliminating the latch-up problem at great cost, allows the systems to live with the problem. It also permits the use of higher supply voltages, resulting in correspondingly higher performance. The proposed scheme is illustrated in the figure. Typical values for T1 and T2 would be T1 = 50 ms T2 = 100 ms. resulting in only 0.05% reduction in system availability. T2 is chosen to be small enough so that no serious damage would be caused to the chip by the large currents due to latch-up. The change in supply voltage, Wv during T1 is where I is the current into the chip. Typical values for I are; Is (stand-by) < 10 mA Is (latch-up) N 50 mA. for C = 1 mF., T1 = 50 ms, WV (standby) = 0.5 mV WV (latch-up) = 2.5 V Clearly, the data stored in the registers will not be affected in the standby mode. However, in the latch-up mode, the voltage will dip sufficiently (1) to reset the latched devices, Vs < V sustain and (2) to be detected by special c...