Browse Prior Art Database

CAM Cell for Use in Hybrid Memory Scheme

IP.com Disclosure Number: IPCOM000041428D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Hou, JC: AUTHOR

Abstract

This article discusses the use of CAM (content-addressable memory) cells in hybrid memories. CAM cells differ from traditional RAM (random-access memory) cells in that in addition to performing a read or a write of a word from or to a given address location, it is content-addressable, that is, it can be accessed by its content. To provide for this extra function, the CAM cell has an extra node which is often referred to as the "match" or "search" line. The logic level on this line is used to indicate the absence or presence of the desired bit. The circuit schematic of the cell is shown in Fig. 1. It consists of a standard six-device static memory cell (T1 to T6) for address storage with three devices (T7 to T9) used for information comparison.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

CAM Cell for Use in Hybrid Memory Scheme

This article discusses the use of CAM (content-addressable memory) cells in hybrid memories. CAM cells differ from traditional RAM (random-access memory) cells in that in addition to performing a read or a write of a word from or to a given address location, it is content-addressable, that is, it can be accessed by its content. To provide for this extra function, the CAM cell has an extra node which is often referred to as the "match" or "search" line. The logic level on this line is used to indicate the absence or presence of the desired bit. The circuit schematic of the cell is shown in Fig. 1. It consists of a standard six-device static memory cell (T1 to T6) for address storage with three devices (T7 to T9) used for information comparison. As mentioned above, there are three modes of operation of the cell, namely, read and store into the cell and search for a given bit, i.e., content addressing. For convenience, these modes will be referred to as READ, WRITE and SEARCH in this discussion. During the SEARCH mode, the match line of the cell, which is precharged high, is either pulled down or remains high. By definition a HIGH on this line after the address comparison indicates a "match" (the address present in the cell is at the same logic level as the input address) and a LOW indicates a "mismatch" (the address stored in the cell is not the same as the input address). Thus, if rows of cascaded cells are formed as shown in Fig. 2, a "mismatch" on just one cell in an entry or row will indicate that the address segment stored in the cells is not similar to the input address segment. Therefore, only a "match" on every bit would yield the desired result. The input address line VT and its complement VF in the cell are both low before the start of the content search. The read/write line remains low during this entire mode of operation. To illustrate how the cell works assume that a logical ONE is stored in the cell; this corresponds to node T high. As VT starts to rise since node F is low (T7 is turned off), no charge flows through T7 to charge up the gate of T9. The match line retains its charge and indicates a "match" for this bit. On the other hand, if VF rises, then because T8 is turned on, charge flows through to the gate of T9.

T9 turns on and the match line is discharged to indicate a "mismatch." Since the performance of the search mode depends on the speed at which this line discharges, T9 has a rather large width-to-length ratio. A point to note here is that in t...