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Busy Bit Concept for Two-Port Memory

IP.com Disclosure Number: IPCOM000041429D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 13K

Publishing Venue

IBM

Related People

Dill, FH: AUTHOR

Abstract

This publication describes a busy bit concept for a two-port memory. This technique involves the addition of one bit per word on the two-port memory for providing an internal handshake mechanism whereby access control is passed. This mechanism also provides a means of having highly encoded memory protection. The quasi-two-port memory was originally proposed as a means of supporting bit mapped displays. In this mode the secondary port is read-only and the primary port is a conventional read/write port. This is satisfactory for displays which are an output device and which do not modify the contents of the file they are displaying. It is clear that the concept of a second asynchronous port is very powerful outside of the display arena, particularly if the second port can be made read/write.

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Busy Bit Concept for Two-Port Memory

This publication describes a busy bit concept for a two-port memory. This technique involves the addition of one bit per word on the two-port memory for providing an internal handshake mechanism whereby access control is passed. This mechanism also provides a means of having highly encoded memory protection. The quasi-two-port memory was originally proposed as a means of supporting bit mapped displays. In this mode the secondary port is read-only and the primary port is a conventional read/write port. This is satisfactory for displays which are an output device and which do not modify the contents of the file they are displaying. It is clear that the concept of a second asynchronous port is very powerful outside of the display arena, particularly if the second port can be made read/write. Then the port can serve both input and output applications, such as are needed for communication and supporting DASD (direct-access storage device). In these applications, the asynchronous capability of the Q2-M design is particularly useful in that it obviates the need for FIFO (first-in, first-out) devices or double buffers for synchronization. The ability to access a memory freely from two independent ports raises the question of who is in charge. This disclosure proposes a mechanism for sorting this question out. It also provides a means of having very highly encoded memory protection, which may also be useful. If one considers 64k-bit memory chip technology, the memory words usually contain 256 bits. If we include a 257th bit which is brought directly to an output pin without decoding, this bit can be used as a busy bit. It can be set to one by the CPU when the memory word is handed to the secondary port for a write operation. When the secondary port has completed the requested write, it sets the bit to zero, which is read in during the transfer of that word into the memory array. Thus, wh...