Browse Prior Art Database

Salicide Process for Silicide Wiring by Cvd

IP.com Disclosure Number: IPCOM000041431D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Roberts, S: AUTHOR

Abstract

This article describes a method for making self-aligned silicide structures ("salicides") using LPCVD (low pressure chemical vapor deposition) to deposit tungsten (W) and using WF6 as a carrier gas to chemically react with the Si surface and to preclean the surface to promote surface reaction and minimize the deposition of W over the sidewall oxide spacers and other oxide covered areas. Existing methods for fabricating salicide structures encounter problems which are due to the non-uniform surface reactivity with "nominally clean" Si surfaces. They require high temperatures (in excess of 800ŒC) for a complete reaction with the Si, which also results in bridging between closely spaced lines, due to lateral diffusion of the Si during the thermally induced reaction with the overlying metal.

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Salicide Process for Silicide Wiring by Cvd

This article describes a method for making self-aligned silicide structures ("salicides") using LPCVD (low pressure chemical vapor deposition) to deposit tungsten (W) and using WF6 as a carrier gas to chemically react with the Si surface and to preclean the surface to promote surface reaction and minimize the deposition of W over the sidewall oxide spacers and other oxide covered areas. Existing methods for fabricating salicide structures encounter problems which are due to the non-uniform surface reactivity with "nominally clean" Si surfaces. They require high temperatures (in excess of 800OEC) for a complete reaction with the Si, which also results in bridging between closely spaced lines, due to lateral diffusion of the Si during the thermally induced reaction with the overlying metal. This problem becomes more severe by the normally close proximity of the polysilicon gate electrode to the source and drain diffusion in current small geometry FET devices. The presently described method eliminates the above-noted problems by using the following processing steps: 1. forming a polysilicon gate structure using conventional techniques; 2. depositing W at a sufficiently low rate using a hot wall LPCVD with WF6 as a carrier gas modified to

promote surface reaction over exposed Si surfaces, thereby

limiting the presence of W only on Si surfaces; 3. interdiffusing W and Si to form the WSi2 layer on the desired surfaces, using...