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CMOS Exclusive or Circuit

IP.com Disclosure Number: IPCOM000041467D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Craig, WJ: AUTHOR

Abstract

An exclusive OR circuit is implemented in complementary metal-oxide-semiconductor (CMOS) technology which uses N channel transfer gates or transistors and which requires only six devices, three P channel devices P1, P2 and P3 and three N channel devices N1, N2 and N3, with the use of a very small amount of direct current power. As seen in the figure, if only A or B is high, i.e., a 1, node N is low and, therefore, the output is high. If both A and B are low, the voltage VH from the supply terminal is applied to node N, turning off P3 and turning on N3, dropping the output to ground. If both A and B are high, the voltage at node N reaches VH minus the threshold voltage (VT) of N1 or N2. This voltage VH-VT will turn on N3 but it may not be high enough to completely turn off P3.

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CMOS Exclusive or Circuit

An exclusive OR circuit is implemented in complementary metal-oxide- semiconductor (CMOS) technology which uses N channel transfer gates or transistors and which requires only six devices, three P channel devices P1, P2 and P3 and three N channel devices N1, N2 and N3, with the use of a very small amount of direct current power. As seen in the figure, if only A or B is high, i.e., a 1, node N is low and, therefore, the output is high. If both A and B are low, the voltage VH from the supply terminal is applied to node N, turning off P3 and turning on N3, dropping the output to ground. If both A and B are high, the voltage at node N reaches VH minus the threshold voltage (VT) of N1 or N2. This voltage VH-VT will turn on N3 but it may not be high enough to completely turn off P3. However, to ensure that P3 is completely turned off to permit the output to go to ground, P3 is fabricated so as to have a low threshold voltage, e.g., -2.0 volts. This low threshold voltage may be readily produced with the addition of one mask for providing a deep implant into P3. It can be seen that even though transfer gates N1 and N2 are N channel devices, full switching of the inverter devices P3 and N3 is provided in this exclusive OR circuit. Although an exclusive OR circuit has been illustrated, it can be seen that similar techniques may be used on other circuits, such as latches, to reduce the number of N and P channel devices.

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