Browse Prior Art Database

Trench-Isolated Field-Effect Transistors

IP.com Disclosure Number: IPCOM000041469D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 65K

Publishing Venue

IBM

Related People

Rideout, VL: AUTHOR

Abstract

Field-effect transistors made in the complementary metal oxide semiconductor (CMOS) technology or in the N channel metal oxide semiconductor (NMOS) technology utilize trench isolation and self-registering gate contacts to fabricate field-effect transistor (FET) integrated circuits. For purposes of illustration, a basic four-mask NMOS FET process is described. As illustrated in Fig. 1, which is a plan view, and Fig. 2, which is a sectional view taken through line 2-2 of Fig. 1, a channel region threshold adjust is performed in P type semiconductor layer 10 in a known manner followed by successive layers: a gate dielectric layer 12 of silicon dioxide, a layer 14 of doped polysilicon, an oxide pad layer 16 and a nitride oxidation-resistant layer 18.

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Trench-Isolated Field-Effect Transistors

Field-effect transistors made in the complementary metal oxide semiconductor (CMOS) technology or in the N channel metal oxide semiconductor (NMOS) technology utilize trench isolation and self-registering gate contacts to fabricate field-effect transistor (FET) integrated circuits. For purposes of illustration, a basic four-mask NMOS FET process is described. As illustrated in Fig. 1, which is a plan view, and Fig. 2, which is a sectional view taken through line 2-2 of Fig. 1, a channel region threshold adjust is performed in P type semiconductor layer 10 in a known manner followed by successive layers: a gate dielectric layer 12 of silicon dioxide, a layer 14 of doped polysilicon, an oxide pad layer 16 and a nitride oxidation-resistant layer 18. With the use of a first mask, the polysilicon layer 14 is formed into an elongated gate electrode 14'. N+ source and drain regions 20 and 22, respectively, are implanted or diffused with, preferably, arsenic. A thick layer 23 of silicon dioxide is then grown over the entire surface of substrate 10 except under the gate electrodes 14' to form a very planar structure. By using a second mask, trench-isolation regions 24 and 26 are defined, etched and filled with an insulating material 28, such as sputtered or deposited oxides or nitrides, as indicated in Fig. 3, which is a plan view, and Fig. 4, which is a sectional view taken along line 4-4 of Fig. 3. Immediately after etching and prior to filling trenches 24 and 26 with insulating material 28, a thin protective oxide layer 30 is grown in trenches 24 and 26 to protect the walls thereof. After depositing a passivating layer 31 over the entire structure, a third mask is used to open contact holes to N+ source region 20 and gate electrode 14' to provide contact 32 for metal line 34 and contact 36 for polysilicon regions 38, as illustrated in Fig. 5. A fourth mask is used to define the metal line patterns illustrated in Figs. 5 and 6, where Fig. 6 is a sectional view taken through line 6-6 of Fig. 5. It should be noted that the contact-to-gate electrode 14' is self- registering or misalignment-tolerant; however, diffusion contact 32 i...