Browse Prior Art Database

High Gain, Cross-Coupled Sense Amplifier

IP.com Disclosure Number: IPCOM000041472D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 48K

Publishing Venue

IBM

Related People

Park, H: AUTHOR

Abstract

A fast cross-coupled sense amplifier is provided which has high gain or sensitivity and high resolution. The sense amplifier, illustrated in the figure, includes a latch 10 having driver transistors Q1 and Q2 and load transistors Q3 and Q4, which may be of the N channel depletion type, as shown, or of the P channel enhancement type, connected to a voltage source VH of, e.g., 5 volts. Latch 10 is formed by applying a set latch signal SL to the control electrodes of a set latch pair of transistors Q5 and Q6. A pair of bit/sense lines B/S1 and B/S0 are connected to the control electrodes of driver transistors Q1 and Q2, respectively.

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High Gain, Cross-Coupled Sense Amplifier

A fast cross-coupled sense amplifier is provided which has high gain or sensitivity and high resolution. The sense amplifier, illustrated in the figure, includes a latch 10 having driver transistors Q1 and Q2 and load transistors Q3 and Q4, which may be of the N channel depletion type, as shown, or of the P channel enhancement type, connected to a voltage source VH of, e.g., 5 volts. Latch 10 is formed by applying a set latch signal SL to the control electrodes of a set latch pair of transistors Q5 and Q6. A pair of bit/sense lines B/S1 and B/S0 are connected to the control electrodes of driver transistors Q1 and Q2, respectively. A memory cell 12, including a storage capacitor CS and a switching transistor Q9, has a current-carrying electrode connected to bit/sense line B/S1 and a control electrode connected to a word line WL1. A dummy cell 14, including a dummy cell capacitor CD and a switching transistor Q10, has a current-carrying electrode connected to bit/sense line B/S0 and a control electrode connected to a dummy word line DL. A pair of precharge transistors Q7 and Q8 are connected between a resolving potential source VR, having a voltage magnitude about one half of that of VH, and bit/sense lines B/S1 and B/S0, respectively with their control electrodes connected to a precharge pulse terminal PC. DATA and DATA terminals are connected through bit switch transistors Q11 and Q12 to the control electrodes of driver transistors Q1 and Q2, respectively. An equalizing device, such as transistor Q13, is connected between the bit/sense lines B/S1 and B/S0. In operation, data is introduced into, say, storage cell CS of memory cell 12, in a known manner by applying appropriate pulses to the bit/sense lines B/S1 and B/S0 through the bit switch transistors Q11 and Q12 with the word line WL1 turned on, and the dummy cell 14 has a half charge stored in dummy cell capacitor CD by turning on equalizing transistor Q13 and dummy word line DL when one of the bit/sense lines B/S1 and B/S0 has 5 volts applied thereto and the other line has zero volts.

After information is stored in cell 12, e.g., a 1 binary digit is stored with storage capacitor CS having a full charge, precharge pulse PC of 5 volts turns on precharge transistors Q7 and Q8, applying 2.5 volts to bit/sense lines B/S1 and B/S0, with the voltage at nodes N1 and N2 charging up to VQ of about 2 to 3 volts, whic...