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Edge-Triggered Sampling Logic Circuit for Synchronous Systems

IP.com Disclosure Number: IPCOM000041491D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 24K

Publishing Venue

IBM

Related People

Cartman, F: AUTHOR

Abstract

This logic circuit samples a data input and provides a data output with low skew with respect to an input gate that runs continuously at one-half the rate of the synchronous speed of the system. It is useful in applications which require a wide data valid "window" from data which may be highly skewed. Alternative methods require a clock pulse to sample and latch the highly skewed data to present a wide data valid "window". It is often difficult to propagate a narrow clock pulse and to fit it entirely under highly skewed data. A typical embodiment of the logic circuit is shown in Fig. 1. Fig. 2 shows the (idealized) waveforms involved. The logic shown in Fig. 1 follows the general form of Boolean Algebra defined below: Therefore, for Fig. 1: 1. Output = 0 = ( A + I ) .

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Edge-Triggered Sampling Logic Circuit for Synchronous Systems

This logic circuit samples a data input and provides a data output with low skew with respect to an input gate that runs continuously at one-half the rate of the synchronous speed of the system. It is useful in applications which require a wide data valid "window" from data which may be highly skewed. Alternative methods require a clock pulse to sample and latch the highly skewed data to present a wide data valid "window". It is often difficult to propagate a narrow clock pulse and to fit it entirely under highly skewed data. A typical embodiment of the logic circuit is shown in Fig. 1. Fig. 2 shows the (idealized) waveforms involved. The logic shown in Fig. 1 follows the general form of Boolean Algebra defined below: Therefore, for Fig. 1: 1. Output = 0 = ( A + I ) . ( B + I ) = A B + B I + A I = B I + A I which states that when the input gate is high, latch A is at the output, and that when the input gate is low, latch B is at the output. 2. Except for a 3-logic block delay: D = I F = I which states that when I is low, A is passing the data-in and B is latched with the data-in that was present 3 logic block delays after I went low. The opposite is true when I goes high. In summary: a. When I goes low,

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