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Diagnosis of Self-Test Failures

IP.com Disclosure Number: IPCOM000041493D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 4 page(s) / 56K

Publishing Venue

IBM

Related People

McAnney, WH: AUTHOR

Abstract

The technique uses signature superposition and is applicable to any self-test structure containing a repetitive pattern generator and a separate linear fault signature register, as shown in Fig. 1. In test mode, a parallel random pattern source 22 is used to broadside load the SRLs (shift register latches) 16 of each logic chip 10 on a module with pseudorandom stimuli. Following a sequential cycling of the machine clocks to capture the test results, the SRLs 16 are unloaded into a multiple input signature register (MISR) 24, simultaneously loading the next set of pseudorandom stimuli from the source 22. Each test can be symbolically represented by Scan, C1, C2, ..., Cn, where Scan represents the parallel loading (and simultaneous unloading) of stimuli into the SRLs and where Ci represents toggling of machine clock i.

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Diagnosis of Self-Test Failures

The technique uses signature superposition and is applicable to any self-test structure containing a repetitive pattern generator and a separate linear fault signature register, as shown in Fig. 1. In test mode, a parallel random pattern source 22 is used to broadside load the SRLs (shift register latches) 16 of each logic chip 10 on a module with pseudorandom stimuli. Following a sequential cycling of the machine clocks to capture the test results, the SRLs 16 are unloaded into a multiple input signature register (MISR) 24, simultaneously loading the next set of pseudorandom stimuli from the source 22. Each test can be symbolically represented by Scan, C1, C2, ..., Cn, where Scan represents the parallel loading (and simultaneous unloading) of stimuli into the SRLs and where Ci represents toggling of machine clock i. A pass or fail indication is obtained after the last test by comparing the signature remaining in the MISR with the expected signature. The principle of signature superposition is applicable in this structure because the MISR is linear. Linearity means that the response of the MISR to the sum of multiple inputs is the same as the sum of its responses to the individual inputs. A simplified example is shown in Fig. 2. On the left is a two- input MISR being driven by the bit streams shown from two chips, A and B. With a starting value of 0 in both SRLs, the final signature in the MISR after loading the 12 bits IS 0 1. In the upper right of Fig. 2 is shown the MISR collecting the signature of chip A alone, with a constant logical 0 on the chip B input. The final chip A signature is 1 0. Similarly, in the lower right is shown the collection of the final 1 1 signature of chip B. The combined signature is seen to be the bitwise sum (modulo 2) of the signatures for chip A and chip B. Thus, given the individual signatures for each of the chips in such a structure, it is easy to calculate, using superposition, the signature for any subset of the chips or for the whole module. Analogously, the principle of signature superposition may also be applied to the individual SRLs within a chip. Given the MISR signature for each SRL in a chip, the signature for any subset of SRLs or for the whole chip can be calculated using superposition. Fig. 3 shows an elementary example. At the top of Fig. 3 is shown a 2-bit MISR which is initialized to zero. The upper MISR input is a constant logical 0. The lower MISR input is driven by a chip containing 3 SRLs, A, B and C. Four tests are applied. In each test, 3 bits of data are captured in the 3 SRLs and subsequently loaded into the MISR. In the example shown, test T1 captures 001 in SRLS A, B, AND C, respectively, and loads these bits to the MISR. After the 4 tests shown, the final MISR signature is 0 1. THE bottom portion of Fig. 3 shows the individual SRL signatures.

The signature of SRL A, 1 1, is obtained by repeating the 4 tests (again initializing the MISR to...