Browse Prior Art Database

Digitally Controlled Analog Ramp Generator

IP.com Disclosure Number: IPCOM000041495D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Marsh, RW.: AUTHOR

Abstract

This article teaches a ramp generator that can maintain the accuracy and ease of programming of a staircase generator while virtually eliminating the differential linearity error noise produced by the staircase digital-to-analog converter (DAC). The heart of the circuit is an analog integrator 10 which can be switched to a unity-gain inverting amplifier by a relay 11. One DAC 16 supplies the integration current and thus sets the nominal ramp rate and direction. A second DAC 12 is set up as a staircase generator. A feedback circuit samples the difference between the staircase voltage and the ramp voltage. That difference amplified by a second amplifier 20 creates a small correction current for the integrator 10. Amplifier 10 is a high-performance integrator held in the quiescent state by relay 11, which is normally closed.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

Digitally Controlled Analog Ramp Generator

This article teaches a ramp generator that can maintain the accuracy and ease of programming of a staircase generator while virtually eliminating the differential linearity error noise produced by the staircase digital-to-analog converter (DAC). The heart of the circuit is an analog integrator 10 which can be switched to a unity-gain inverting amplifier by a relay 11. One DAC 16 supplies the integration current and thus sets the nominal ramp rate and direction. A second DAC 12 is set up as a staircase generator. A feedback circuit samples the difference between the staircase voltage and the ramp voltage. That difference amplified by a second amplifier 20 creates a small correction current for the integrator 10. Amplifier 10 is a high-performance integrator held in the quiescent state by relay 11, which is normally closed. The gain of amplifier 10 from a staircase DAC 12 is set at exactly -1 by the resistors 13 and 14 coupled to the relay 11. Thus, the starting voltage of the ramp may be programmed by presetting the up-down counter 15 and the staircase DAC 12 to the desired value. The ramp rate must be programmed in two places, i.e., the ramp DAC 16 and the pulse train oscillator 17. For the values shown and using twelve-bit DACs, 10 V on the ramp DAC with a pulse train period of one millisecond (staircase least significant bit = 5 mV) will produce a ramp of 5 V/s. Programming a number, equal to the number of desired pulses, into the pulse train oscillator 17 causes the pulse train to begin, relay 11 to energize, amplifier 10 to integrate, and a sample/hold 18 to hold. The number selected is the quantity of staircase steps desired and hence determines the stop voltage relative to the start voltage. The sign of the pulse quantity determines the sign of the slope of the staircase w...