Browse Prior Art Database

In-Phase and Out-Phase Push-Pull Latch Off-Chip Driver

IP.com Disclosure Number: IPCOM000041511D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Freeman, LB: AUTHOR [+3]

Abstract

This article describes two bipolar transistor latch circuits used for high performance off-chip driving. Both circuits have push-pull drive capability (active transistor pull-up and pull-down) with one providing a non-inverting (true) data output and the other providing inverted (complement) data output. Fig. 1 shows a block diagram of the inverting latch-driver, illustrating the overall logical function of the circuit. Fig. 2 shows the actual circuit schematic. The circuit comprises a pair of collector dotted current switches with an emitter dotted push-pull output stage. Fig. 3 shows the clock timings: The latch is closed, and data is held when -CLK is high and +CLK is low. New data is supplied to the "data" input. -CLK goes low, +CLK goes high, and the data is gated into the latch and appears at the output.

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In-Phase and Out-Phase Push-Pull Latch Off-Chip Driver

This article describes two bipolar transistor latch circuits used for high performance off-chip driving. Both circuits have push-pull drive capability (active transistor pull-up and pull-down) with one providing a non-inverting (true) data output and the other providing inverted (complement) data output. Fig. 1 shows a block diagram of the inverting latch-driver, illustrating the overall logical function of the circuit. Fig. 2 shows the actual circuit schematic. The circuit comprises a pair of collector dotted current switches with an emitter dotted push-pull output stage. Fig. 3 shows the clock timings: The latch is closed, and data is held when -CLK is high and +CLK is low. New data is supplied to the "data" input. -CLK goes low, +CLK goes high, and the data is gated into the latch and appears at the output. -CLK goes high, +CLK goes low, the latch is closed, and data is held. Fig. 4 shows a block diagram of the non-inverting latch-driver, illustrating the overall function of the circuit. Fig. 5 shows the actual circuit schematic. The circuit comprises a pair of collector dotted current switches, emitter dotted emitter followers and a push-pull output stage. Fig. 6 shows the clock timings: a) The latch is closed, and data is held when -CLK is high and +CLK is low. b) New data is supplied to the "data" input. c) -CLK goes low, +CLK goes high and the data is gated into the latch and appears at the output. d)...