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CMOS Schmitt Trigger Circuit

IP.com Disclosure Number: IPCOM000041514D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Craig, WJ: AUTHOR

Abstract

A Schmitt trigger circuit is formed in complementary metal-oxide-semiconductor (CMOS) technology which uses a regenerative feedback circuit to modify the transfer characteristics of the input inverter which provides readily controllable detection points upon the rise and fall of the input signal. This Schmitt trigger circuit has improved performance and small size and uses very little power. As indicated in the figure, with the voltage at terminal IN low, P channel transistor P1 turns on along with N channel transistor N2 and P channel transistor P2, with N channel transistor N1 and P channel transistor P3 being off. Thus, the voltage at node Q- is high and the voltage at output node Q is low.

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CMOS Schmitt Trigger Circuit

A Schmitt trigger circuit is formed in complementary metal-oxide-semiconductor (CMOS) technology which uses a regenerative feedback circuit to modify the transfer characteristics of the input inverter which provides readily controllable detection points upon the rise and fall of the input signal. This Schmitt trigger circuit has improved performance and small size and uses very little power. As indicated in the figure, with the voltage at terminal IN low, P channel transistor P1 turns on along with N channel transistor N2 and P channel transistor P2, with N channel transistor N1 and P channel transistor P3 being off. Thus, the voltage at node Q- is high and the voltage at output node Q is low. When the voltage at terminal IN goes high, N1 turns on and P1 turns off; thus, the voltage at node Q- decreases toward ground turning off N2 and turning on P3 which raises the output voltage at terminal Q. The high voltage at terminal Q causes P2 to also turn off. It can be seen that the hysteresis or Schmitt trigger action is supplied by P2 with its gate electrode driven by the opposite state of node Q that is, the inverter output formed by P1, P2 and N1 having two transfer curves.

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