Browse Prior Art Database

High Performance Twin-Cell Memory Array

IP.com Disclosure Number: IPCOM000041515D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Scheuerlein, RE: AUTHOR [+2]

Abstract

In a twin-cell memory array wherein signals are stored in potential wells, the time required for sensing is considerably shortened by providing a substantially zero threshold voltage device between adjacent potential storage wells, which avoids cell position sensitivity. A twin-cell memory array is described in, e.g., U.S. Patent 4,040,016. By merely discharging unselected word lines to ground potential and allowing them to float, information stored in the cells along the unselected word lines is prevented from being disturbed.

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High Performance Twin-Cell Memory Array

In a twin-cell memory array wherein signals are stored in potential wells, the time required for sensing is considerably shortened by providing a substantially zero threshold voltage device between adjacent potential storage wells, which avoids cell position sensitivity. A twin-cell memory array is described in, e.g., U.S. Patent 4,040,016. By merely discharging unselected word lines to ground potential and allowing them to float, information stored in the cells along the unselected word lines is prevented from being disturbed. As shown in the figure, which is a sectional view taken through a word line 10 of the array, a first twin cell 12 has a first storage capacitor 14 which includes a first bit/sense line B1L and a first N diffusion region 16 having a thin dielectric layer 17 interposed therebetween and a second storage capacitor 18 which includes a second bit/ sense line B1R and a second N diffusion region 20 also having layer 17 interposed therebetween. Regions 16 and 20 are disposed at the surface of semiconductor substrate 21 made of P type material. A word line charge transfer device 23 including segment 10A of word line 10 and channel region 22, located at the surface of substrate 21, is disposed between the first and second storage capacitors 14 and 18. A plurality of other similar twin cells, including cell 24, are disposed along word line 10. Cell 24 includes bit/sense lines BNL and BNR and N diffusion regions 26 and 28 with charge transfer device 30 including word line segment 10N and channel region 32 disposed between N diffusion regions 26 and 28. Channel regions 34 and 36 are disposed at the surface of substrate 21 between adjacent twin cells. Channel regions 22, 32, 34 and 36 are fabricated so as to provide a threshold voltage of substantially zero volts. First and second N+ diffusion regions 38 and 40, connected to a pulse source terminal PS, act alternately as a source of electrons and as a charge drain when a zero voltage or a positive voltage of, say, VH = +5 volts, is applied thereto. P regions 42 and 44 are formed to provide enhancement devices each having a voltage threshold of about +1 volt. Connected to one end of word line 10 is a word line driving circuit 46 having a transistor T1, connected between word line 10 and a word line pulse source OWL, and a transistor T2, connected between a word line decoder (not shown) and the control electrode of transistor T1, the control electrode of transistor T1 also being connected to word line 10 through a bootstrap capacitor
C.

The control electrode of transistor T2 is connected to a voltage supply terminal VH . Connected between the other end of word line 10 and a point of reference potential is transistor T3 having its control electrode connected to a word line grounding pulse terminal OWLG . In the operation of the array, it is assumed initially that the bit/sense lines B1L, B1R, BNL and BNR are precharged to voltage VH, t...