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Browse Prior Art Database

Pattern-Independent Memory Array

IP.com Disclosure Number: IPCOM000041516D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Scheurlein, RE: AUTHOR [+2]

Abstract

A memory array having a plurality of twin cells coupled to a word line has a boron implant between adjacent twin cells to increase the voltage threshold of the transfer device disposed between adjacent cells to eliminate or at least reduce data pattern sensitivity. A version of the twin cell array is disclosed in the preceding article and the basic twin cell concept is taught in U.S. Patent 4,040,016. Pattern sensitivity in the worst case is understood to mean the tendency of two cells substantially midway between two N+ diffusion regions, which act as sources of electrons, to develop signals more slowly than cells located closer to the N+ diffusion regions when the cells along a word line store half 1 and half 0 digits of binary information, i.e., 111---1100---000 or 000---0011---111.

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Pattern-Independent Memory Array

A memory array having a plurality of twin cells coupled to a word line has a boron implant between adjacent twin cells to increase the voltage threshold of the transfer device disposed between adjacent cells to eliminate or at least reduce data pattern sensitivity. A version of the twin cell array is disclosed in the preceding article and the basic twin cell concept is taught in U.S. Patent 4,040,016. Pattern sensitivity in the worst case is understood to mean the tendency of two cells substantially midway between two N+ diffusion regions, which act as sources of electrons, to develop signals more slowly than cells located closer to the N+ diffusion regions when the cells along a word line store half 1 and half 0 digits of binary information, i.e., 111---1100---000 or 000---0011- --111. The pattern sensitivity has been found to be due to either an excess of charge in two adjacent filled potential wells or a dearth of charge in two adjacent relatively empty potential wells. In either situation charge must move along the entire length of the word line between the N+ diffusion regions before the signal in the cells develops fully. As seen in the figure, which is a sectional view taken through a word line 10, first cell 12 includes a first storage capacitor 14 formed by bit/sense line B1L and N diffusion region 16 in semiconductor substrate 18 and a second storage capacitor 20 formed by bit/sense line B1R and N diffusion region 22, with channel region 24 disposed between regions 16 and 20 being adjusted to provide transfer device 25, located between first and second storage capacitors 14 and 20, with a threshold voltage of substantially zero volts. Second cell 26 is similarly arranged with first storage capacitor 28 including bit/sense line B2L and N diffusion 30 and second storage capacitor 32 including bit/sense line B2R and N diffusion region 34, with channel region 35 disposed between regions 30 and 34 being adjusted to provide a zero threshold voltage transfer device 37. Third cell 36 includes first capacitor 38 having bit/sense line B3L and N diffusion 40 and second capacitor 42 having bit/sense line B3R and N diffusion region 44, with channel region 45 disposed between regions 40 and 44 being adjusted to provide a zero voltage threshold transfer device 47. N+ diffusion regions 46 and 48, which a...