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Pass-Transistor-Circuit-Failure Analysis

IP.com Disclosure Number: IPCOM000041530D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Roth, JP: AUTHOR [+3]

Abstract

Pass transistors are a common form of transistor for very large-scale integration (VLSI). Their functional behavior is substantially different from that of bipolar technologies, and the question of their diagnosis requires a new analysis. First, there is an analysis of the behavior without failure of primitive transistor configurations, which are sufficient to cover any pass-transistor design. Next, the D-algorithm is adapted 1 Ùto compute tests, when they exist, for failures. For this purpose, tests of length 2 are derived for some failures, which could not be tested in one wave. Pass transistors are special field-effect transistors, widely planned for use in VLSI. Their behavior differs substantially from those represented by "logic gates"; for example, the bare transistor has a kind of memory.

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Pass-Transistor-Circuit-Failure Analysis

Pass transistors are a common form of transistor for very large-scale integration (VLSI). Their functional behavior is substantially different from that of bipolar technologies, and the question of their diagnosis requires a new analysis. First, there is an analysis of the behavior without failure of primitive transistor configurations, which are sufficient to cover any pass-transistor design. Next, the D-algorithm is adapted 1 Ùto compute tests, when they exist, for failures. For this purpose, tests of length 2 are derived for some failures, which could not be tested in one wave. Pass transistors are special field-effect transistors, widely planned for use in VLSI. Their behavior differs substantially from those represented by "logic gates"; for example, the bare transistor has a kind of memory. Thus, the first task is to analyze the behavior of correctly functioning pass transistor networks. Some primitive configurations are illustrated in the figures, whose combination would suffice to form ANY network, and make a functional analysis of them, in terms of the regular notation, R-notation. Finally, there is an adaptation of the D-algorithm [1] to the task of computing tests for their failures. In the following description, each pass transistor is considered to have input, output, and control variables, which describe its behavior (Fig. 1). Each such variable v may assume the values of 1, 0, x (x standing for an unknown value or state) and v*, the latter standing for the previous state of the variable. In the pass-transistor networks illustrated, it is assumed that they are unidirectional and, further, that inverters are appropriately inserted to insure this, without actually showing them in the diagrams. A pass-transistor network may be represented as an interconnection of the primitive configurations, as shown in Figs. 1 - 4. It is further assumed that the design is acyclic, that is, no feedback, so that there will be no memory except that provided by each pass transistor. In the pass-transistor network defined here, it is necessary to define some variables as primary inputs (PIs) and other variables as primary outputs (POs); for analysis or diagnostic purposes it is sufficient [1] to assume that there is just one primary output. In the analysis it is necessary that the state of each pass transistor be defined in terms of its present and last state. This means assumption of a clock and that combinational behavior necessarily is defined for each pass transistor in terms of two waves of inputs. Fig. 5 is a simple example of a pass-transistor network. In Fig. 5, lower case letters are used for variables and upper case, for their negations: for example, the negate of a would be denoted A. Diagnosis of Failures in Pass-Transistor Networks Consider Fig. 1. In this case, it is simple to test primary input u or output v: for u stuck at 1, the pattern u=0 and k=1 is applied. This will give at the...