Browse Prior Art Database

High Speed Emitter Coupled Logic Counter

IP.com Disclosure Number: IPCOM000041534D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Grasso, LJ: AUTHOR [+2]

Abstract

A programmable synchronous counter capable of operating at a clock rate of about 250 MHz is disclosed. Existing designs for high frequency counters emphasize minimization of hardware and generality of use. Typically, the counter uses standard master-slave flip-flops with all outputs buffered to yield a high number of fan-outs. This factor results in a decrease in the maximum operating frequency. Fig. 1 is a block diagram of one bit of the counter and is composed of four independent latches to create a master-slave latch with a toggle enable and a reset input. The counter bit is arranged as two separate master-slave flip-flops so that QM and Q-M, the master flip-flop outputs, are generated essentially simultaneously and the slave sections can be immediately clocked.

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High Speed Emitter Coupled Logic Counter

A programmable synchronous counter capable of operating at a clock rate of about 250 MHz is disclosed. Existing designs for high frequency counters emphasize minimization of hardware and generality of use. Typically, the counter uses standard master-slave flip-flops with all outputs buffered to yield a high number of fan-outs. This factor results in a decrease in the maximum operating frequency. Fig. 1 is a block diagram of one bit of the counter and is composed of four independent latches to create a master-slave latch with a toggle enable and a reset input. The counter bit is arranged as two separate master-slave flip-flops so that QM and Q-M, the master flip-flop outputs, are generated essentially simultaneously and the slave sections can be immediately clocked. This arrangement also eliminates one gate delay since an OR/NOR phase splitter can be omitted. When T- and C- are low and C is high, QM and Q are toggled from the previous state since QS and Q-S update the master section. The slave section will update with the next C- high and C low. Fig. 2 is a circuit diagram of a particular embodiment of the principles illustrated in Fig. 1. Each gate labeled E is wired as an emitter dot, and each gate labeled C is wired as a collector dot. This wiring further reduces the number of gates required, further increasing the speed. All the inputs of the flip-flops are active low; T- is the toggle enable, C- is the clock, D and D correspond to -SQ and QS, respectively, of the slave flip-flops, and C, the slave clock, is the complement of C and is also active low. In order for any flip-flop to toggle, the toggle input and the clock must be low. For any toggle to be low, all previous Q-S must be low. Reset takes place when C and R are active low, and R is active high. This forces FF0 at QM to reset to the low state, while FF1 at Q-M sets t...