Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Process Simplification of Bipolar Structure With Specific Fabrication Advantages

IP.com Disclosure Number: IPCOM000041541D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Fabricius, KA: AUTHOR [+4]

Abstract

A polysilicon base contact for decreased capacitance along with dielectric isolation are desirable for high performance bipolar devices. A process is described in which several problems involved with advance bipolar transistor processing are resolved while decreasing the total number of processing steps. A thick recessed oxide isolation (ROI) is employed in most bipolar structures to decrease wiring channel capacitance and as a dielectric isolation when butting junctions. The ROI masking material must prevent oxygen diffusion without causing damage to the silicon surface. A structure which would minimize the "bird's beak" is also desirable. The ROI masking level defines the silicon areas of the active device regions.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

Process Simplification of Bipolar Structure With Specific Fabrication Advantages

A polysilicon base contact for decreased capacitance along with dielectric isolation are desirable for high performance bipolar devices. A process is described in which several problems involved with advance bipolar transistor processing are resolved while decreasing the total number of processing steps. A thick recessed oxide isolation (ROI) is employed in most bipolar structures to decrease wiring channel capacitance and as a dielectric isolation when butting junctions. The ROI masking material must prevent oxygen diffusion without causing damage to the silicon surface. A structure which would minimize the "bird's beak" is also desirable. The ROI masking level defines the silicon areas of the active device regions. This silicon area is later uncovered using standard lithography, at which point a polysilicon extrinsic base may be deposited and lithographically defined. A single process is hereinafter described in which a stack consisting of silicon dioxide, polysilicon, and chemically vapor deposited (CVD) silicon nitride serve as both an ROI diffusion mask and an extrinsic base polysilicon contact. An example of a typical bipolar structure fabrication using the aforementioned techniques is as follows: 1. An ROI mask stack consisting of approximately 100 nanometers of silicon dioxide 10, about 350 nanometers of P+ doped polysilicon 11, and approximately 200 nanometers of CVD silicon nitride 12 are deposited on N-type epitaxy 13 wafers having a subcollector 14 and substrate 15. 2. Standard lithography techniques are used to define the ROI and silicon base areas. A trench pattern is etched by a dry etch, such as CF4 reactive ion etching (RIE), for example. 3. Following a photoresist strip, the exposed silicon in the trench patt...