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High Density Silicon Gate Process

IP.com Disclosure Number: IPCOM000041553D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 101K

Publishing Venue

IBM

Related People

Beyer, KD: AUTHOR [+2]

Abstract

The spacing between the storage capacitor and the gate in single-layer polysilicon FET arrays is determined by the resolution of the optical lithography or E-beam technology. This article describes a process which can form spacings of less than 0.5 micron between the polysilicon capacitor and the polysilicon gate independent of lithography. For two-cell designs with a shared bit line, a four-sided borderless contact can be fabricated. The process is shown in Figs. 1 through 12. The introduction of the narrow space between capacitor and gate is described in Figs. 2 through 6. A P-silicon surface area 10 is isolated by recessed oxide isolation (ROX). A gate silicon dioxide layer 11 is thermally grown upon the surface of silicon body 10.

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High Density Silicon Gate Process

The spacing between the storage capacitor and the gate in single-layer polysilicon FET arrays is determined by the resolution of the optical lithography or E-beam technology. This article describes a process which can form spacings of less than 0.5 micron between the polysilicon capacitor and the polysilicon gate independent of lithography. For two-cell designs with a shared bit line, a four- sided borderless contact can be fabricated. The process is shown in Figs. 1 through 12. The introduction of the narrow space between capacitor and gate is described in Figs. 2 through 6. A P-silicon surface area 10 is isolated by recessed oxide isolation (ROX). A gate silicon dioxide layer 11 is thermally grown upon the surface of silicon body 10. A N doped polysilicon layer 12, silicon dioxide layer 13, silicon nitride layer 14 and polysilicon layer 15 are formed thereover and in that order. The thickness of the gate oxide layer 11 can vary between 250 and 500 A, of the N doped polysilicon layer 12 between 2000 and 5000 A, of the chemical vapor deposited (CVD) SiO2 layer 13 between 3000 and 5000 A of the Si3N4 layer 14 between 1500 and 3000 A, and of the polysilicon layer 15 between 250 and 350 A An island consisting of CVD SiO2 layer 13, Si3N4 layer 14 and polysilicon layer 15 is formed by conventional lithography and etching techniques above the capacitor and "gate" polysilicon layer, as shown in Fig. 2. The size of the polysilicon gate area is determined by the size of this island. Referring to Fig. 3, a thin N doped, approximately 300 A thick polysilicon layer 16, a 300 to 500 A-A thick CVD Si3N4 layer 17 and a 2000 to 5000 A CVD SiO2 layer 18 are deposited over the island structure. The thickness of the CVD SiO2 layer 18 determines the spacing between the polysilicon capacitor and gate. The silicon dioxide sidewall is formed by a timed anisotropic CF4/H2 reactive ion etch (RIE) to produce the Fig. 4 structure. The SiO2 sidewall 18 is removed in buffered HF and the underlying Si3N4 sidewall 17 remains. An ap...