Browse Prior Art Database

Transparent I/O Isolation - I/O Isolation in Fixed Metal

IP.com Disclosure Number: IPCOM000041562D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 48K

Publishing Venue

IBM

Related People

Graf, MC: AUTHOR [+2]

Abstract

Transparent I/O Isolation (TIOI) is a set of guidelines that produces a testable, mixed function masterslice on an open part number basis. The masterslice designer: (a) defines circuits, circuit locations, and fixed wire; (b) defines the I/O's involved in array testing; (c) specifies the appropriate delay paths through the array and I/O ports. Fig. 1 depicts a typical structure for an address or data-in port. For every input to the array, there must exist two inputs: system (S) and test (T). For every test input to the array there exists a unique receiver, hereafter referred to as an array test receiver (ATR). As shown in the diagram, a fixed wire connection exists between a C4 (I/O solder pad) and an ATR, and between an ATR and the test input to the array.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

Transparent I/O Isolation - I/O Isolation in Fixed Metal

Transparent I/O Isolation (TIOI) is a set of guidelines that produces a testable, mixed function masterslice on an open part number basis. The masterslice designer: (a) defines circuits, circuit locations, and fixed wire; (b) defines the I/O's involved in array testing; (c) specifies the appropriate delay paths through the array and I/O ports. Fig. 1 depicts a typical structure for an address or data-in port. For every input to the array, there must exist two inputs: system (S) and test (T). For every test input to the array there exists a unique receiver, hereafter referred to as an array test receiver (ATR). As shown in the diagram, a fixed wire connection exists between a C4 (I/O solder pad) and an ATR, and between an ATR and the test input to the array. The user has access to the ATR used for address or data-in, with no restrictions. A driver may share the same C4 with an ATR used for address or data-in if: (i) that driver has two inputs (system and test) and the test input places the driver into its uncontrolling state (UCS); (ii) the input to the driver is controlled by TM1 (a test mode control line). The system and test inputs to the array are controlled by TM1. That is, the array will accept the input of either system or test depending on the state of TM1. Note that all system inputs are user-defined. Fig. 2 shows the output configuration of the array. Here, we define an array test driver (ATD) as a driver with two inputs - system (S) and test (T). An ATD is controlled by a test mode control line (here, TM2) that determines which input to the driver is accepted. Note the fixed metal structure from the output of the array to a unique test input of an ATD. A receiver can share the same C4 pad with an ATD used for data-out if the receiver is not an ATR. Fig. 3 shows the control line structure. Here, two more test mode command lines are involved: TM3 and TM4. The structure is similar to that previously described for address and data. The exception here is that there is a fixed metal line from the system input of the command lines of the array to the test input of an ATD controlled by TM4. The following rules apply: 1. The ATR used for control lines cannot be accessed by the user; 2. An ATD can share the same C4 with the control ATR if: a) the ATD's test input is tied to the driver's uncontrolling state; b) the ATD is controlled by TM3; 3. The ATD used for the system control lines cannot share a C4 with a receiver. The test mode control lines are generated as shown in Fig. 4. It is required that two inputs (TMI1 and TMI2) be dedicated for test mode control. As shown in Figs. 5A, 5B, 5C, 5D, TIOI has four basic modes of ope...