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Method for Implementing a High Speed Adapter

IP.com Disclosure Number: IPCOM000041571D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Beaucousin, JC: AUTHOR [+2]

Abstract

This article is related to a method for providing one high speed link by multiplexing a plurality of lower speed links. The method consists in generating N slots of P bits in a time division multiplexer (TDM) connected to P lower speed links in order for N-slot frames to be transmitted on the high speed link to a time division demultiplexing unit where the received bits are assigned to P lower speed links. In a frame the first slot S0, which is devoted to the synchronization, comprises m bits, m-1 bits being assigned to the synchronization pattern and one bit being assigned to synchronization loss information. The following slots S1 to SN-1 are data bit slots. In each data bit slot, bits from the P links are sequentially arranged, each bit being devoted to one assigned link.

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Method for Implementing a High Speed Adapter

This article is related to a method for providing one high speed link by multiplexing a plurality of lower speed links. The method consists in generating N slots of P bits in a time division multiplexer (TDM) connected to P lower speed links in order for N-slot frames to be transmitted on the high speed link to a time division demultiplexing unit where the received bits are assigned to P lower speed links. In a frame the first slot S0, which is devoted to the synchronization, comprises m bits, m-1 bits being assigned to the synchronization pattern and one bit being assigned to synchronization loss information. The following slots S1 to SN-1 are data bit slots. In each data bit slot, bits from the P links are sequentially arranged, each bit being devoted to one assigned link. Due to the synchronization slot S0, the bit rate on the high speed link is not exactly the product of P times the bit rate on each lower speed link. In order not to impair this rate, N is chosen as a function of P in such a way that (N-1) x P Z cte where CTE represents the constant. The receiving demultiplexing unit is considered as synchronized when three successive synchro slots have been detected. In order to recover as quickly as possible the synchronization on the receiving end when a synchronization loss is detected, the information "synchro loss" is transmitted to the emitting TDM. Upon receipt of the "synchro loss" information the transmitt...