Browse Prior Art Database

Effective Execution of Multicycle Instruction in One Processor Cycle

IP.com Disclosure Number: IPCOM000041584D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 37K

Publishing Venue

IBM

Related People

Pomerene, JH: AUTHOR [+4]

Abstract

The effective execution time of a multicycle instruction, such as a Store Multiple Instruction (STM), is reduced to one processor cycle by a procedure in which a copy of the general-purpose registers (GPRs) which is maintained on the cache module is validated in one processor cycle, leaving the processor free to act upon the next instruction in the following cycle. The remaining storage activity relating to the STM is performed asynchronously within the cache module without requiring additional processor cycles for their execution.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

Effective Execution of Multicycle Instruction in One Processor Cycle

The effective execution time of a multicycle instruction, such as a Store Multiple Instruction (STM), is reduced to one processor cycle by a procedure in which a copy of the general-purpose registers (GPRs) which is maintained on the cache module is validated in one processor cycle, leaving the processor free to act upon the next instruction in the following cycle. The remaining storage activity relating to the STM is performed asynchronously within the cache module without requiring additional processor cycles for their execution. For a processor with a 64-byte (64B) cache bandwidth and a 64B cache line, the STM can be executed by a single line swap in one cycle, as described above, if the following conditions C1, C2 and C3 are met: C1 - All 16 GPRs are stored in order C2 - The address of the STM is a 64B boundary C3 - A copy of the GPR's current contents is maintained in the cache module (a 64B register) and is available be swapped into the identified 64B cache line. If it should happen that not all of these conditions can be met, this does not necessarily mean that more than one processor cycle will be needed to execute the STM. As will be described later, some relaxation of the conditions can be permitted in certain cases without increasing the effective execution time. In accordance with this procedure, the execution of the STM is accomplished in two phases, 0/1 and 0/2. During 0/1 the GPR contents and cache module status are checked to determine whether execution of the STM can be completed asynchronously within the cache module without requiring additional processor cycles. If all of the conditions C1, C2 and C3 are met, this is assured, and 0/2 is initiated immediately. If C3 cannot be met because there are other storage actions pending in the cache module at that time, then 0/2 of the STM execution must be deferred until such other actions are completed. This increases the effective execution time of STM. C3 requires that all changes to the GPR be stored in the cache module in a timely manner. If conditions C1 and C2 are not met, it still may be possible to accomplish effective execution of the STM in one processor cycle by utilizing a Source-Sink data interchange technique within the cache module which effectively satisfies C1 and C2. In this case different portions of the cache module serve as Sour...