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MTL/I2L Memory Cell

IP.com Disclosure Number: IPCOM000041587D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Heimeier, H: AUTHOR [+4]

Abstract

The memory cell consists of two cross-coupled basic MTL/I2L inverter stages forming a flip-flop. Each inverter stage comprises a lateral, injecting PNP transistor and a vertical, inverting NPN transistor. The drawing shows the basic layout of one memory cell section of a memory array. The lateral PNP transistor comprises a P zone 1 with an injector contact IC and a P zone 2 which are diffused in an N layer 3. N layer 3 forms the N base of the PNP transistor as well as the emitter of the NPN transistor. P zone 2 forms the collector of the PNP transistor as well as the base of the NPN transistor and comprises a top collector contact TC within a collector zone of the NPN transistor and a base contact of the NPN transistor.

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MTL/I2L Memory Cell

The memory cell consists of two cross-coupled basic MTL/I2L inverter stages forming a flip-flop. Each inverter stage comprises a lateral, injecting PNP transistor and a vertical, inverting NPN transistor. The drawing shows the basic layout of one memory cell section of a memory array. The lateral PNP transistor comprises a P zone 1 with an injector contact IC and a P zone 2 which are diffused in an N layer 3. N layer 3 forms the N base of the PNP transistor as well as the emitter of the NPN transistor. P zone 2 forms the collector of the PNP transistor as well as the base of the NPN transistor and comprises a top collector contact TC within a collector zone of the NPN transistor and a base contact of the NPN transistor. By dielectric trench isolation zones 4, abutting upon or even partly overlapping P zones 1 and 2, each stage is isolated from the other, which completes the flip-flop. A problem is that along the edges of isolation zones 4 in the area of the N base of the PNP transistor, an inversion channel is generated which forms a leakage current path between the emitter and collector of the PNP transistor. This leads to a drop in the current amplification, thus impairing the function of the memory cell. By an N+ guard ring diffusion 5, crossing the trench isolation zones 4 and protruding into the N base, the inversion channel is cut off, thus preventing parasitic coupling between the emitter and collector of the PNP transistor. For this pu...