Browse Prior Art Database

Trench Node One-Device Memory Cell Process

IP.com Disclosure Number: IPCOM000041601D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 72K

Publishing Venue

IBM

Related People

El-Kareh, B: AUTHOR [+3]

Abstract

A process for making a memory cell having one switching device for coupling to a trench-type storage node provides reduced bit/sense line capacitance, sensitivity to radiation-induced soft errors, hot electron injection and junction leakage while increasing the storage node capacitance, breakdown voltage, punch-through voltage and sustaining voltage. The steps of the process include depositing a first layer 10 of silicon dioxide, preferably chemically vapor deposited, over a semiconductor substrate 12 having a P-conductivity and a <100> crystallographic orientation. A first layer 14 of photoresist is deposited over silicon dioxide layer 10 and an opening or trench 16 is formed in substrate 12 by known techniques. Boron is then ion implanted into region 18 at the bottom of trench 16, as indicated in Fig. 1.

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Trench Node One-Device Memory Cell Process

A process for making a memory cell having one switching device for coupling to a trench-type storage node provides reduced bit/sense line capacitance, sensitivity to radiation-induced soft errors, hot electron injection and junction leakage while increasing the storage node capacitance, breakdown voltage, punch-through voltage and sustaining voltage. The steps of the process include depositing a first layer 10 of silicon dioxide, preferably chemically vapor deposited, over a semiconductor substrate 12 having a P-conductivity and a <100> crystallographic orientation. A first layer 14 of photoresist is deposited over silicon dioxide layer 10 and an opening or trench 16 is formed in substrate 12 by known techniques. Boron is then ion implanted into region 18 at the bottom of trench 16, as indicated in Fig. 1. Photoresist layer 14 is then removed, as is the silicon dioxide layer 10, with a dip-etch process. As shown in Fig. 2, a layer 20 of N+ doped oxide is deposited over the surface of substrate 12 and into trench 16, followed by a second layer 22 of photoresist. By using known reactive ion etching techniques, photoresist layer 22 is removed except for segment 22' in trench 16. Doped oxide layer 20, where exposed, is removed with only segment 20' in trench 16 remaining, as shown in Fig. 3. Photoresist layer segment 22' is now removed and the dopant in doped oxide layer segment 20 is driven into substrate 12 to form N+ region 24. A barrier layer 26, preferably 200 angstroms of cobalt silicide (CoSi2), is formed on the surface of substrate 12, a thicker layer 28 of N+ doped silicide, preferably titanium silicide (TiSi2), is deposited over barrier layer 26, and a second layer 30 of chemically vapor deposited silicon dioxide is deposited over doped silicide layer 28. Openings 32 and 34 are then formed in silicon dioxide layer 30 and doped silicide layer 28 by known techniques including a reactive ion etching process to define medium doped N+ source and drain regions 36 and 38 which are formed after...