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Bypass Circuit for Receiver and Driver Delay Measurement

IP.com Disclosure Number: IPCOM000041605D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Daghir, KS: AUTHOR [+2]

Abstract

The disclosed circuit technique enables the measurement of the additional access delays introduced into the signal path during testing of an embedded array. Fig. 1 is a block diagram showing the testing scheme of an embedded array with access delay DA . Two control signals, T1 at an up level and T2 at a down level, are provided to isolate the array from the logic inputs and outputs during testing. After testing, T1 is set to the Down level and T2 to the Up level in order to allow the logic inputs and outputs to reach the embedded array. Usually the tester signal will go through a receiver with delay DR, the array with delay DA, AND-INVERTER (AIG) with delay DG, and a driver with delay DD . The total delay DT measured is DT = DR + DA + DG + DD The additional delays, DR, DG and DD, have to be measured accurately.

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Bypass Circuit for Receiver and Driver Delay Measurement

The disclosed circuit technique enables the measurement of the additional access delays introduced into the signal path during testing of an embedded array. Fig. 1 is a block diagram showing the testing scheme of an embedded array with access delay DA . Two control signals, T1 at an up level and T2 at a down level, are provided to isolate the array from the logic inputs and outputs during testing. After testing, T1 is set to the Down level and T2 to the Up level in order to allow the logic inputs and outputs to reach the embedded array. Usually the tester signal will go through a receiver with delay DR, the array with delay DA, AND-INVERTER (AIG) with delay DG, and a driver with delay DD . The total delay DT measured is DT = DR + DA + DG + DD The additional delays, DR, DG and DD, have to be measured accurately. Disclosed is a bypass circuit to the embedded array that enables the measurement of these additional delays, DR, DG and DD . It is comprised of a TTL (transistor-transistor logic) 2-way AND INVERTER, AIL, which is identical to AIG . It is controlled by an externally provided voltage, TL, to make or break the bypass, as shown in Fig. 1. This bypass circuit is placed between nodes A and B of Fig. 1. In order to measure the delay of the loop consisting of a driver, AIL and a receiver, the following conditions are set: T1 at Down level T2 at Down level TL at Up level For normal testing mode: T1 at Up lev...