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Saturated CTS Memory Cell Using a PNP Load

IP.com Disclosure Number: IPCOM000041611D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Dorler, JA: AUTHOR [+4]

Abstract

A static memory cell is typically a circuit which employs feedback to attain one of two stable states. The simplest circuit which meets this criteria is a pair of cross-coupled transistors. Additions to this configuration form various memory cells. Harper cells use additional emitters and resistor loads to form the complete circuit. CTS cells use PNP loads and Schottky barrier diodes (SBDs) for reading/writing. (The Complementary Transistor Switch (CTS) cell is fully described in the article "A 1024-Byte ECL Random Access Memory Using a Complementary Transistor Switch (CTS) Cell" by J. A. Dorler, J. M. Mosley, G. A. Ritter, R. O. Seeger and J. R. Struk, IBM Journal of Research and Development 25, 126-134 (May 1981). Disclosed is an unclamped CTS-type cell. Many present array cells are SBD-protected against saturation.

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Saturated CTS Memory Cell Using a PNP Load

A static memory cell is typically a circuit which employs feedback to attain one of two stable states. The simplest circuit which meets this criteria is a pair of cross-coupled transistors. Additions to this configuration form various memory cells. Harper cells use additional emitters and resistor loads to form the complete circuit. CTS cells use PNP loads and Schottky barrier diodes (SBDs) for reading/writing. (The Complementary Transistor Switch (CTS) cell is fully described in the article "A 1024-Byte ECL Random Access Memory Using a Complementary Transistor Switch (CTS) Cell" by J. A. Dorler, J. M. Mosley, G. A. Ritter, R. O. Seeger and J. R. Struk, IBM Journal of Research and Development 25, 126-134 (May 1981). Disclosed is an unclamped CTS-type cell. Many present array cells are SBD-protected against saturation. This was clearly needed when the number of cells was small, the transistors were large, and the currents were large to accommodate high speed at high capacitances. This results in long delays for cell saturation in the absence of the SBD clamps. However, now with better processes and improved lithography, the saturation capacitance of the cell can be equal to or less than the metal line capacitance of the array. With the advent of improved circuit designs and very low standby currents (typically >5 mA) the SBDs are no longer required. What is being disclosed here is the removing of the clamp SBD from the ar...