Browse Prior Art Database

Complementary Push-Pull Driver

IP.com Disclosure Number: IPCOM000041616D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Pollmann, K: AUTHOR [+4]

Abstract

A monolithic integrated complementary push-pull driver is proposed. It prevents noise voltages at the parasitic inductances Lp of the power supply lines by simultaneously switching complementary output stages, to which identical loads are applied from outside the semiconductor chip. The driver stage, shown in the figure, consists of a first push-pull driver comprising the NPN transistors T1 to T3 and the resistors R1 to R3, and of a second push-pull driver comprising the NPN transistor T4, the two PNP transistors T5 and T6 and the resistors R4 to R6. The base of T4 is connected to the base of T1 by a Schottky diode D1. The layout of the driver stage must be such that there is a maximum parasitic capacitance (represented by capacitor C in the figure) between the epitaxial layer and the substrate.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

Complementary Push-Pull Driver

A monolithic integrated complementary push-pull driver is proposed. It prevents noise voltages at the parasitic inductances Lp of the power supply lines by simultaneously switching complementary output stages, to which identical loads are applied from outside the semiconductor chip. The driver stage, shown in the figure, consists of a first push-pull driver comprising the NPN transistors T1 to T3 and the resistors R1 to R3, and of a second push-pull driver comprising the NPN transistor T4, the two PNP transistors T5 and T6 and the resistors R4 to R6. The base of T4 is connected to the base of T1 by a Schottky diode D1. The layout of the driver stage must be such that there is a maximum parasitic capacitance (represented by capacitor C in the figure) between the epitaxial layer and the substrate. The outputs O1 and O2 of the first and the second push-pull driver, respectively, are connected to one signal line each which connects the chip with the driver to another chip with a receiver. The stray capacitance of each signal line is subjected to the same load CL1 and CL2, respectively. Through lines 1 and 2 with the parasitic inductances Lp1 and Lp2, the semiconductor chip with the driver is connected to the operating voltage source. Noise voltages, occurring at the parasitic line inductances Lp1 and Lp2 during the switching of the output stages, are prevented as follows: An up-level signal, applied to driver input I, makes T1 conductive. As a result, the base current supply to T2 is stopped, making T2 non-conductive and T3 conductive. If T1 is conductive, T4 is non- conductive, so that T5 becomes conductive. T5 draws its increasing output current from capacitor C. The path for this current extends from the upper electrode of capacitor C,...