Browse Prior Art Database

Frequency Determinator

IP.com Disclosure Number: IPCOM000041625D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Bustamante, LA: AUTHOR

Abstract

This article describes a technique for determining whether a power supply connected to a machine is 50 hertz or 60 hertz. This enables the optimization of machine timing signals to the zero-cross signal of the power supply. The technique used is to set a counter upon the occurrence of a first zero cross to expire before the occurrence of the next 50 hertz zero cross and after the occurrence of the next 60 hertz zero cross. In that manner, the frequency is determined. Fig. 1 shows the major hardware components used by this technique. No attempt is made to illustrate all details of the overall system.

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Frequency Determinator

This article describes a technique for determining whether a power supply connected to a machine is 50 hertz or 60 hertz. This enables the optimization of machine timing signals to the zero-cross signal of the power supply. The technique used is to set a counter upon the occurrence of a first zero cross to expire before the occurrence of the next 50 hertz zero cross and after the occurrence of the next 60 hertz zero cross. In that manner, the frequency is determined. Fig. 1 shows the major hardware components used by this technique. No attempt is made to illustrate all details of the overall system. As shown, the processor 10 interfaces with the machine through I/O interface 11 components, which include Control Bytes (CCB01, CCB11 and CCB07) and Status Byte(s) (CSB07), and with memories 12 and 13 via an address bus 14 and data bus 15. In an implementation, the 8-bit interface counter 16 is two 4-bit synchronous counters cascaded together and wired in the countdown mode. To program the counter 16, the processor 10 loads the desired bit pattern onto D1- D7 via the addressable output byte 00D2, i.e., CCB11. Once programmed and loaded, the counter 16 is enabled at line 50 and allowed to decrement at a 7.825 kHz rate by properly initiating signals to bytes 00C6 and 00C0 (CCB07 and CCB01). Fig. 2 illustrates how the software is executed and how it interfaces with the hardware described above. Essentially, the microcode is executed in 'polling' loop fashion. The Zero-Cross Routine 17 shown at the start of the loop monitors the inputs at location 0XC6 (CSB07 in Fig. 1) until a preset number of zero-cross pulses are detected, for example, two. After the occurrence of two (2) zero-cross pulses, i.e., 20 msecs or 16.66 msecs for a 50 and 60 hertz machine, respectively, execution of the polling loop code 18 is allowed. If an interrupt occurs due to the 8-bit counter 16 reaching a value of zero, control is transferred to the 'interrupt' loop 19, then returned to the appropriate location in the 'polling' loop. If an interrupt does not occur during execution of the polling loop, the HERTZP routine 20 is executed. As can be observed from Fig. 2, the software is broken into two segments, HERTZP 20 and HERTZI 21. HERTZP is executed in the 'polling' loop, and HERTZI during interrupts. Upon entry into Hertz routine 20 upon...