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Josephson Compensating Current Injection Device

IP.com Disclosure Number: IPCOM000041628D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Gheewala, TR: AUTHOR [+3]

Abstract

Current injection devices (CIDs) are known in Josephson technology, and generally comprise an interferometer loop. In order to make the phase difference across the interferometer loop inductance less sensitive to systematic variations in junction Io, part of the interferometer inductance is supplied by Josephson junctions in the interferometer loop. This results in larger operating margins than conventional CIDs, with no loss in density if the compensating CID is placed in the wiring channel. Fig. 1 is a schematic diagram of a compensating CID, while Fig. 2 shows a possible physical layout for the circuit. In Fig. 1, Josephson devices J1 and J2 are in the interferometer loop, while Josephson devices J3 are used to provide part of the interferometer inductance.

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Josephson Compensating Current Injection Device

Current injection devices (CIDs) are known in Josephson technology, and generally comprise an interferometer loop. In order to make the phase difference across the interferometer loop inductance less sensitive to systematic variations in junction Io, part of the interferometer inductance is supplied by Josephson junctions in the interferometer loop. This results in larger operating margins than conventional CIDs, with no loss in density if the compensating CID is placed in the wiring channel. Fig. 1 is a schematic diagram of a compensating CID, while Fig. 2 shows a possible physical layout for the circuit. In Fig. 1, Josephson devices J1 and J2 are in the interferometer loop, while Josephson devices J3 are used to provide part of the interferometer inductance.

To ensure that the device switches at (Ig; Ic) = (I01+I02;0), L1/L2 = I02/I01 and n1/n2 = I02/I01 where n1 and n2 are the respective number of inductor junctions on the branches corresponding to L1 and L2 . In Fig. 1, n1 = 3n2 = 3. The margins on the Ic axis are set by the LI02 product and I03 the value of the inductor junction critical current. The nominal design criterion is where d X Do/2f and k is a coefficient of order unity, chosen to maximize operating margins. The value of I03 > I01, I02 so that the inductor junctions do not switch to the voltage state. If there is a systematic increase in critical current, the phase difference across the inductor junc...