Browse Prior Art Database

Bubble Array Logic

IP.com Disclosure Number: IPCOM000041632D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Chang, H: AUTHOR [+2]

Abstract

Array logic is performed in this invention using conventional bubble storage chips. This contrasts with the prior art, where structures such as decoders and personalization means have been required to perform array logic. Other prior-art structures for performing array logic utilized multiple input compressors and auxiliary devices or associative search elements. This invention uses currently available conventional bubble storage chips for logic operations. As an example, consider a two-bit adder. A and B are the addend bits, and C and D are the augend bits. S0 and S1 are respectively the zero- and first-order sums, and K is the carry.

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Bubble Array Logic

Array logic is performed in this invention using conventional bubble storage chips. This contrasts with the prior art, where structures such as decoders and personalization means have been required to perform array logic. Other prior-art structures for performing array logic utilized multiple input compressors and auxiliary devices or associative search elements. This invention uses currently available conventional bubble storage chips for logic operations. As an example, consider a two-bit adder. A and B are the addend bits, and C and D are the augend bits. S0 and S1 are respectively the zero- and first-order sums, and K is the carry. The equations for S0, S1 and K can be expressed as: S0 = BD + B - -D S1 = A-C + AB- + A - + AC- + A -D + ABCD -B -C -CD -D -BC K = AC + ABD + BCD One effective means for reducing the array size, particularly when the number of inputs is large, is to partition the inputs. For the above example, partitioning is accomplished by factoring the terms: S0 = BD + B - -D S1 = (AC + AC - + D + (A- + AC)BD - -)(B -) -C K = AC + (A + C)BD Note that the product terms are now expressed as functions of variables A and C only, or of the variables B and D only. Referring to Fig. 1, the values of the A-, C- dependent terms are listed as functions of A and C values in the first array; and the values of the B-, D-dependent terms are listed as functions of B and D values in the second array. Consider a hardware implementation using conventional shift registers. The two arrays of values are stored in a shift register array, such as that shown in Fig. 2. Five shift registers store the arrays in their first 8 bits. For example, the term (A-C + AC) is stored in the third shift register. At A = 1 and C = 0, A-C + AC = 0. This value is stored in the third bit position. The term BD is also stored in the third shift register. At B = 1 and D = 0, BD = 0. This value is stored in the seventh bit position. To retrieve the terms, the replicators are activated at the sui...