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Central Processor Retry

IP.com Disclosure Number: IPCOM000041672D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Annunziata, EJ: AUTHOR [+3]

Abstract

A Central Processor (CP) checkpoint retry can be implemented in large scale integration (LSI) technology. The system implementation for CP recovery can be integrated completely in the hardware or partially integrated with the aid of a Service Processor. This description is of a partially integrated design. The design chosen allows the system to continue running when a CP detects an error. Thus, the design is to clockstop only the CP when it gets an error. After the CP is clockstopped and the Service Processor is signalled, the CP is fenced from the System Controller (SC) and the other CPs. The CP is also fenced from the other CPs. This will allow the CP to be scanned. All of the CP rings are scanned and saved for later error analysis. A selected number of arrays are scanned for error analysis.

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Central Processor Retry

A Central Processor (CP) checkpoint retry can be implemented in large scale integration (LSI) technology. The system implementation for CP recovery can be integrated completely in the hardware or partially integrated with the aid of a Service Processor. This description is of a partially integrated design. The design chosen allows the system to continue running when a CP detects an error. Thus, the design is to clockstop only the CP when it gets an error. After the CP is clockstopped and the Service Processor is signalled, the CP is fenced from the System Controller (SC) and the other CPs. The CP is also fenced from the other CPs. This will allow the CP to be scanned. All of the CP rings are scanned and saved for later error analysis. A selected number of arrays are scanned for error analysis. The CP is analyzed to detect storage transfers in process at the time of error. This analysis is unique for a store-in cache system. Directories are updated for fetches not completed. Stores not completed are completed by the Service Processor via a special port to storage. The SC castout register is reset for stores completed. If no castouts, the SC is fenced to inhibit cross interrogates during the purge, since the castout register may be out of synchronism with the CP. The CP is then analyzed for types of errors. Errors may be retriable or not retriable. A dataset representing the system reset state of the CP is scanned in to the CP (with the exce...