Browse Prior Art Database

Write Data Wrap Test

IP.com Disclosure Number: IPCOM000041691D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Danen, JA: AUTHOR [+3]

Abstract

The circuit illustrated in this figure wraps serially encoded data back through the decoder circuit each time a write data operation is performed. The input write data on line 5 is delayed by the circuit 6 for a time period to enable encoding and decoding and is then compared to the output of the decoder circuits 9 by the compare circuit 10 on a real-time basis to check for errors. A "data unsafe" error signal on line 12 is sent to the host, which supplies write data on line 5, when a mismatch is detected to inform the system that an error was detected. In a disk file, this wrap test, when combined with the transition detection in the arm electronics module, virtually guarantees that the data is being properly encoded and written on the disk surface.

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Write Data Wrap Test

The circuit illustrated in this figure wraps serially encoded data back through the decoder circuit each time a write data operation is performed. The input write data on line 5 is delayed by the circuit 6 for a time period to enable encoding and decoding and is then compared to the output of the decoder circuits 9 by the compare circuit 10 on a real-time basis to check for errors. A "data unsafe" error signal on line 12 is sent to the host, which supplies write data on line 5, when a mismatch is detected to inform the system that an error was detected. In a disk file, this wrap test, when combined with the transition detection in the arm electronics module, virtually guarantees that the data is being properly encoded and written on the disk surface. Also passing encoded data through the decode register, allows the decode register 13 to be used as the precompensation register if precompensation is required.

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