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Automatic Center Frequency Adjustment for Phase-Locked Loops

IP.com Disclosure Number: IPCOM000041693D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Call, MG: AUTHOR [+2]

Abstract

A center frequency of a voltage-controlled oscillator (VCO) 10 which is part of a phase-locked loop is set by adjusting the magnitude of the current 1 RFR in a current source connected to the set center frequency terminal of the VCO. The automatic adjustment of the center frequency of the VCO portion of phase-locked loop (PLL) 11 uses a digital-to-analog converter (DAC) 12 to set the current 1RFR as seen in Fig. 2, counter A is set to 0. The nominal Input signal is applied to the phase detector (0 DET) input of PLL 11. Since the VCO 1RFR current is 0, the output of comparator B is high. A logic "1" is applied to the Set Speed input line F. This satisfies AND gate C and causes counter A to increment on the edge of the input signal.

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Automatic Center Frequency Adjustment for Phase-Locked Loops

A center frequency of a voltage-controlled oscillator (VCO) 10 which is part of a phase-locked loop is set by adjusting the magnitude of the current 1 RFR in a current source connected to the set center frequency terminal of the VCO. The automatic adjustment of the center frequency of the VCO portion of phase-locked loop (PLL) 11 uses a digital-to-analog converter (DAC) 12 to set the current 1RFR as seen in Fig. 2, counter A is set to 0. The nominal Input signal is applied to the phase detector (0 DET) input of PLL 11. Since the VCO 1RFR current is 0, the output of comparator B is high. A logic "1" is applied to the Set Speed input line F. This satisfies AND gate C and causes counter A to increment on the edge of the input signal. Counting continues until the output of the low-pass filter D is equal to the reference voltage VR at E, at which time the output of comparator B goes low. This disables AND gate C, preventing any further counting. The low output of comparator B indicates that the center frequency is now set to reference voltage VT and the Set Speed line F can be dropped. Any number of center frequencies can be set within the DAC and VCO operating range.

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