Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Wafer Burn-In

IP.com Disclosure Number: IPCOM000041709D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Reinhart, GR: AUTHOR [+2]

Abstract

Direct current (DC) burn-in at the wafer level is provided by making connections to all common power pads on each chip of a wafer or substrate, then bringing those connections to aluminum or metal lands or conductors placed in dicing channels or kerf regions, and connecting the aluminum lands to large periphery power pads. Contact probes are readily connected to these large power pads. As indicated in Fig. 1, a wafer 10 includes a plurality of complete chips 12 separated by horizontally and vertically arranged dicing channels or kerf regions 14. Around the periphery of the wafer are located incomplete chips 12', some of which, e.g., 12'A, may support a large periphery power pad 16. The periphery pad 16 is connected to a dicing channel aluminum conductor 18, shown in Fig. 2.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

Wafer Burn-In

Direct current (DC) burn-in at the wafer level is provided by making connections to all common power pads on each chip of a wafer or substrate, then bringing those connections to aluminum or metal lands or conductors placed in dicing channels or kerf regions, and connecting the aluminum lands to large periphery power pads. Contact probes are readily connected to these large power pads. As indicated in Fig. 1, a wafer 10 includes a plurality of complete chips 12 separated by horizontally and vertically arranged dicing channels or kerf regions
14. Around the periphery of the wafer are located incomplete chips 12', some of which, e.g., 12'A, may support a large periphery power pad 16. The periphery pad 16 is connected to a dicing channel aluminum conductor 18, shown in Fig. 2. A chip power pad 20 is also connected to aluminum conductor 18 by a metal line 22, as also illustrated in Fig. 2. In the alternative, the chip power pad 20 may be connected to aluminum conductor 18 by a diffusion region 22' at a metal contact 24, as shown in Fig. 3. The contact 24 may include an implant to prevent corrosion to active areas of a chip by creating a PN diode diffusion in the kerf regions 14 adjacent to an associated chip power pad 20 with no direct metallization contact to the active area of the chips. To minimize the number of burn-in chambers, the wafers 10 may be supported on carriers 26 and 26' of the type illustrated in Figs. 4 and 5, respectively. In Fig. 4, the wafers 10 are arranged horizontally with respect to the surface of carrier 26, and in Fig. 5, the wafers 10 are arranged vertically with respect to the surface of carrier 26'. Fig. 6, illustrates in a sectional view taken through line 6-6 of Fig. 4, a contact probe 28 ...