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Multiplexed Addresses for a Two-Card Processor/Memory System

IP.com Disclosure Number: IPCOM000041711D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Livingston, DL: AUTHOR [+3]

Abstract

A computer system can be implemented in which a processor and a memory are contained, respectively, on two cards interconnected by a cable assembly. To reduce system cost and improve signal integrity, it is advantageous to partition the processor/memory system in order to limit the number of signals which are passed between the cards across the cable. It is also advantageous to minimize the number of components in the entire system and to balance these components between the two cards. This improvement in function partitioning is directed to the case in which dynamic random-access memories (DRAMs) are used to implement the memory array. DRAMs require that the row addresses and column addresses by multiplexed before they are latched by the memory chips.

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Multiplexed Addresses for a Two-Card Processor/Memory System

A computer system can be implemented in which a processor and a memory are contained, respectively, on two cards interconnected by a cable assembly. To reduce system cost and improve signal integrity, it is advantageous to partition the processor/memory system in order to limit the number of signals which are passed between the cards across the cable. It is also advantageous to minimize the number of components in the entire system and to balance these components between the two cards. This improvement in function partitioning is directed to the case in which dynamic random-access memories (DRAMs) are used to implement the memory array. DRAMs require that the row addresses and column addresses by multiplexed before they are latched by the memory chips. Normally, there are m row address lines and m column address lines which require an m-bit 2 to 1 multiplexer. If the multiplexer is on the memory card, there must be 2m address lines and other control lines on the cable. By moving the multiplexer to the processor cards, only m address lines, on select line and the remaining control lines are required on the cable. Hence, m-1 cable lines are saved. Other situations may arise, such as a multi-ported memory or different modes of addressing where multiplexing is needed on one or both cards. Since the row address/column address multiplexing is the final stage of multiplexing, it necessarily forces other types...