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Railless Polysilicon Emitter Process

IP.com Disclosure Number: IPCOM000041712D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 88K

Publishing Venue

IBM

Related People

Chu, SSF: AUTHOR [+3]

Abstract

The emitter definition of certain processes is accomplished by reactive ion etching (RIE) in SF6/Cl2 . Etch to end-point detect plus 100% overetch is employed to eliminate rails resulting from the anisotropic RIE. However, this process is not always successful, because the amount of overetch required to remove all the rails is determined by the step height and the slope of the step. In addition, the overetch also removes the insulating layers, e.g., silicon nitride and silicon dioxide, as a result of the finite etch rate ratio in RIE. The following process provides a solution to these problems: 1. The process begins with a multilayer structure upon recessed oxide isolated (ROI) regions 9 and 10 of monocrystalline silicon. The region 9 is to have a base and emitter region formed therein.

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Railless Polysilicon Emitter Process

The emitter definition of certain processes is accomplished by reactive ion etching (RIE) in SF6/Cl2 . Etch to end-point detect plus 100% overetch is employed to eliminate rails resulting from the anisotropic RIE. However, this process is not always successful, because the amount of overetch required to remove all the rails is determined by the step height and the slope of the step. In addition, the overetch also removes the insulating layers, e.g., silicon nitride and silicon dioxide, as a result of the finite etch rate ratio in RIE. The following process provides a solution to these problems: 1. The process begins with a multilayer structure upon recessed oxide isolated (ROI) regions 9 and 10 of monocrystalline silicon. The region 9 is to have a base and emitter region formed therein. The region 10 is to have the collector reach-through region formed therein. The layers over the ROI regions 9 and 10 include chemical vapor deposited (CVD) silicon dioxide underlayer 11, P+ polysilicon layer 12, thermal silicon dioxide layer 13, CVD silicon nitride layer 14, thermal silicon dioxide layer 15, chemical vapor deposited, CVD, silicon nitride layer 16, low temperature silicon dioxide layer 17, and doped polysilicon layer 18. 2. Photolithographically define the emitter area with resist layer 19, as shown in Fig.
1. 3. Plasma etch to remove the exposed polysilicon layer 18 to form the Fig. 2 structure. 4. Remove photoresist to give the Fig. 3 structure. 5. Sidewall etchback by anisotropically etching the horizontal portions of silicon dioxide layer 17 and leave v...