Browse Prior Art Database

Process for Making a Push Plate RAM Cell

IP.com Disclosure Number: IPCOM000041714D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Walker, WW: AUTHOR

Abstract

A process for making a dense, completely self-aligned push plate dynamic random-access memory (RAM) cell uses only a single layer of polysilicon. Figs. 1-5 show a cross-section of two cells during various stages in the process, and Fig. 6 is a top view of the two cells indicating the six masks used to form the cells. As indicated in Fig. 1, a semiconductor substrate 10, after conventional recessed oxide growth (not shown) has a gate oxide 12 of 250 angstroms thickness grown on its surface which is covered by a thin layer of silicon nitride. A photoresist mask (not shown) is then used, along with a suitable etchant for removing a portion of the silicon nitride and gate oxide to define a region 14 under the remaining silicon nitride segment 13 for forming cell transistors.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

Process for Making a Push Plate RAM Cell

A process for making a dense, completely self-aligned push plate dynamic random-access memory (RAM) cell uses only a single layer of polysilicon. Figs. 1-5 show a cross-section of two cells during various stages in the process, and Fig. 6 is a top view of the two cells indicating the six masks used to form the cells. As indicated in Fig. 1, a semiconductor substrate 10, after conventional recessed oxide growth (not shown) has a gate oxide 12 of 250 angstroms thickness grown on its surface which is covered by a thin layer of silicon nitride. A photoresist mask (not shown) is then used, along with a suitable etchant for removing a portion of the silicon nitride and gate oxide to define a region 14 under the remaining silicon nitride segment 13 for forming cell transistors. A combination N- and P implant then defines the cells' storage nodes 16 and 18. The N- impurity preferably has a surface concentration of approximately 5 x 1016cm-3 . With the photoresist mask completely removed, a layer of silicon dioxide 20 is thermally grown to a thickness of about 150 angstroms over storage nodes 16 and 18. A layer of polycide, i.e., a combination doped polysilicon and silicide layer, is deposited over the structure of Fig. 1 and appropriately etched to form storage node plates 22 and 24 and gate electrodes 26 and 28, as shown in Fig. 2. Storage node plates 22' and 24' of third and fourth adjacent cells are also illustrated in Fig. 2. Photoresist mask segments 30 and 32 are provided to protect the openings between plates 22 and 22' and plates 24 and 24', respectively, and then a source/drain arsenic implant is used to provide Nsourc...