Browse Prior Art Database

Timing Optimization at LSSD Design Boundary

IP.com Disclosure Number: IPCOM000041730D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Pauport, A: AUTHOR [+2]

Abstract

In logic circuitry using the level sensitive scan design (LSSD) technique, the cycle time utilization is optimized by entering in the second latch L2 of the shift register latches (SRLs) and exiting directly from the first L1 latch of SRL at the boundary of the LSSD logic. In the LSSD technique, the only type of storage element allowed in a logic design is an SRL comprising a pair of polarity hold latches with the output of the first latch L1 permanently connected to the data input of a second latch L2. The LSSD logic is structured as shown in the drawing and is controlled by C and B clock signals. With regular timing the time used to load the L2 latch is not useful for combinatorial logic; the signal entering the SRL must be available at C clock time, and the signal exiting the SRL will not be available until B clock time.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 95% of the total text.

Page 1 of 2

Timing Optimization at LSSD Design Boundary

In logic circuitry using the level sensitive scan design (LSSD) technique, the cycle time utilization is optimized by entering in the second latch L2 of the shift register latches (SRLs) and exiting directly from the first L1 latch of SRL at the boundary of the LSSD logic. In the LSSD technique, the only type of storage element allowed in a logic design is an SRL comprising a pair of polarity hold latches with the output of the first latch L1 permanently connected to the data input of a second latch L2. The LSSD logic is structured as shown in the drawing and is controlled by C and B clock signals. With regular timing the time used to load the L2 latch is not useful for combinatorial logic; the signal entering the SRL must be available at C clock time, and the signal exiting the SRL will not be available until B clock time. The timing of signal at the boundary of the LSSD design is improved as follows: The SRL latch is used in such a way that the latch L2 is directly loaded with the incoming signal either by using a direct L2 input or by forcing active the L1 latch clock input. The SRL latch is outputted from the latch L1 to generate the outgoing signal. This organization facilitates chip testing by offering two configurations: 1) functional configurations where the SRLs are interconnected through combinatorial logic, and 2) testing configurations where the SRLs are connected with each other into a single shift register...