Browse Prior Art Database

ECL to NMOS Receiver

IP.com Disclosure Number: IPCOM000041735D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Hoover, RA: AUTHOR [+2]

Abstract

The ECL (Emitter Coupled Logic) Receiver is a device which provides the chip designer with a simple means of translating ECL voltage level signals (typically between -3.0 and 0.0 volts) to NMOS voltage levels on board the NMOS chip itself. The circuit requires no special mask steps to fabricate. In addition, there is no need for any supply. The circuit can be added to existing NMOS designs easily and will displace any off-chip circuitry which is currently used to provide ECL to NMOS voltage translation. ECL circuitry is used primarily in high-speed applications, since typical gate propagation delays are less than 2 ns. Real-time processing functions as well as fast floating point arithmetic operations are often implemented in the technology for this reason.

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ECL to NMOS Receiver

The ECL (Emitter Coupled Logic) Receiver is a device which provides the chip designer with a simple means of translating ECL voltage level signals (typically between -3.0 and 0.0 volts) to NMOS voltage levels on board the NMOS chip itself. The circuit requires no special mask steps to fabricate. In addition, there is no need for any supply. The circuit can be added to existing NMOS designs easily and will displace any off-chip circuitry which is currently used to provide ECL to NMOS voltage translation. ECL circuitry is used primarily in high-speed applications, since typical gate propagation delays are less than 2 ns. Real-time processing functions as well as fast floating point arithmetic operations are often implemented in the technology for this reason. The speed advantage of ECL is not obtained without a sacrifice, however. The power consumed by a typical ECL gate is greater than 20 mw, as compared to the 1 to 2 mw consumption of an NMOS gate. The significance of this is that the power consumed limits the circuit densities which can be obtained on a given chip. If circuit densities are held to a relatively low level, then systems must use more parts to maintain function. Since increased part counts contribute to system reliability failures, systems designers are then obliged to compromise between maintaining system operating speeds and keeping part counts as low as possible. One way to maintain system speed while limiting chip count is to use ECL circuits only for the most speed-critical operations and take advantage of high density NMOS designs for those which are not so critical. This approach works well provided some efficient means of communication can be established between ECL and NMOS chips. The typical "true" level of an ECL device is at -0.75 volt. The typical "fal...