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Memory Address Driver Noise Compensation Method

IP.com Disclosure Number: IPCOM000041737D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Wortzman, D: AUTHOR

Abstract

A method is described for wiring an array card in such a way as to minimize the effect of the coupling noise between adjacent address pins in array modules. The method can be described with the help of Figs. 1 and 2. Fig. 1 shows the wiring of typical address lines on an array card. Depicted are three address bits which drive three adjacent pins on several modules. For each address, the two drivers are used in order to reduce the loading per driver. The top driver is "true", and the lower driver is the address "complement". This is done to reduce the simultaneous switching of each driver. The three "true" drivers are connected to modules 1-6, and the "complement" drivers are connected to modules 7-12. Each capacitor represents the coupling capacitance between the adjacent array module pins.

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Memory Address Driver Noise Compensation Method

A method is described for wiring an array card in such a way as to minimize the effect of the coupling noise between adjacent address pins in array modules. The method can be described with the help of Figs. 1 and 2. Fig. 1 shows the wiring of typical address lines on an array card. Depicted are three address bits which drive three adjacent pins on several modules. For each address, the two drivers are used in order to reduce the loading per driver. The top driver is "true", and the lower driver is the address "complement". This is done to reduce the simultaneous switching of each driver. The three "true" drivers are connected to modules 1-6, and the "complement" drivers are connected to modules 7-12. Each capacitor represents the coupling capacitance between the adjacent array module pins. Coupling capacitance, as in the case of capacitance to ground, slows the driver transition. However, when the adjacent pins are switched opposite to the driver transition, the effective coupling capacitance doubles. Fig. 2 shows Fig. 1 rewired to minimize the effect of coupling capacitance. It should be noted that no matter which way the outside address pin drivers switch, the resultant coupling to the center address pin driver is zero. This reduction in effective capacitance reduces the driver delay significantly in each memory cycle, using typical dynamic RAMs where there are two address cycles (Row Address Select and Column Ad...