Browse Prior Art Database

Planarization of Conductor Surfaces

IP.com Disclosure Number: IPCOM000041741D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Goubau, WM: AUTHOR

Abstract

In multilayer circuitry, the planar coating of each layer over the circuitry is facilitated by providing space-filling conductors so that a wiring pattern, as in Fig. 1, is provided with space-filling conductors essentially evenly spaced, as in Fig. 2. The viscosity requirements of the coating material are relaxed.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Planarization of Conductor Surfaces

In multilayer circuitry, the planar coating of each layer over the circuitry is facilitated by providing space-filling conductors so that a wiring pattern, as in Fig. 1, is provided with space-filling conductors essentially evenly spaced, as in Fig.
2. The viscosity requirements of the coating material are relaxed.

1

Page 2 of 2

2

[This page contains 1 picture or other non-text object]