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Interface Between a Central Control Unit and Its Service Processor

IP.com Disclosure Number: IPCOM000041813D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 1 page(s) / 13K

Publishing Venue

IBM

Related People

Caudrillier, JC: AUTHOR [+4]

Abstract

In a data processing system wherein a service processor (SP) is attached to a central control unit (CCU), a hardware and software interface has to be provided to insure communication between the service processor and the central control unit. The interface lines comprise data and address bus lines and control lines. The address bus is used by the SP to send register addresses to the CCU. The data are exchanged between the SP and the CCU one byte at a time through the data bus. A write strobe signal is gated when no parity error is detected on the data/address buses and allows the addressed CCU register to be written. A read strobe signal is also gated when no parity error is detected on the data/address buses and allows the addressed CCU register to be gated on the data bus.

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Interface Between a Central Control Unit and Its Service Processor

In a data processing system wherein a service processor (SP) is attached to a central control unit (CCU), a hardware and software interface has to be provided to insure communication between the service processor and the central control unit. The interface lines comprise data and address bus lines and control lines. The address bus is used by the SP to send register addresses to the CCU. The data are exchanged between the SP and the CCU one byte at a time through the data bus. A write strobe signal is gated when no parity error is detected on the data/address buses and allows the addressed CCU register to be written. A read strobe signal is also gated when no parity error is detected on the data/address buses and allows the addressed CCU register to be gated on the data bus. Read acknowledgement and write acknowledgement signals are returned by the CCU to the SP. A SP inoperative line is set ON by the SP to allow the SP interface to be degated by the CCU which sends a SP inoperative level 1 interrupt request to the control program, for preventing a failure in the SP processor from being propagated to the CCU. High level and low level interrupt request lines are set ON by the CCU to present interrupts to the SP when necessary. An interface parity check line is used for reporting a parity error on data/address buses. This interface is controlled by the service processor through direct operation, indirect operations and LSSD (Level Sensitive Scan Design) operations. The only operations initiated by the CCU are interrupts presented to the SP. Using direct operations, the CCU registers are directly addressed by the interface address lines and access to these registers is obtained...