Browse Prior Art Database

Real Time Diagnostic Logging and Analysis

IP.com Disclosure Number: IPCOM000041814D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 72K

Publishing Venue

IBM

Related People

Broadbent, ST: AUTHOR

Abstract

A signal-handling unit, such as peripheral equipment to a host processor, employs error detection and correction circuits for detecting errors and correcting detected errors. When such signal-handling units become prone to high error rates, even with the error detection and correction capabilities, signal data patterns are logged in real time and multiplexed with the corrected signal data such that diagnostic analysis close to real time and employing normal signal-handling operations is provided.

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Real Time Diagnostic Logging and Analysis

A signal-handling unit, such as peripheral equipment to a host processor, employs error detection and correction circuits for detecting errors and correcting detected errors. When such signal-handling units become prone to high error rates, even with the error detection and correction capabilities, signal data patterns are logged in real time and multiplexed with the corrected signal data such that diagnostic analysis close to real time and employing normal signal- handling operations is provided. When a host processor is employed, a data reduction program analyzes the multiplexed diagnostic data for generating error information useful for reducing the error-prone conduction, creates histograms for facilitating, diagnostic maintenance, and can provide further correction capabilities for correcting the data that could be miscorrected by the signal- handling unit. A data source, such as a communication link, peripheral data storage device, unit record equipment, keyboarding equipment, video equipment, and the like, provides input data having interleaved error-correction code (ECC) redundancies for detecting and correcting errors in the data. Further, a cyclic redundancy check (CRC) can be appended to various blocks of data for detecting errors not detected by ECC and for detecting miscorrected errors. The input data can be in a serial form provided over a single data channel, or can be provided over a plurality of independent data channels. In a serial implementation, blocks of data are defined in terms of time slots on the single data channel; while in the parallel-channel embodiment, the various parallel channels provide a first level of block identification, with time slotting providing a second level of data-block identification scheme. The input data in many instances is digitally modulated for facilitating operation of the data source. Such digital modulation can include M of N codes, and the like. A code converter receives the input data and converts the in-coded data to a binary form without data-source-related redundancies. The binary data from the code converter is suppled through a delay circuit to an error corrector which receives error patterns (EP) for correcting the data using known ECC techniques. The error patterns EP are generated through a set of error syndrome generators and error pattern generators, known in the art. Error correction is enhanced through the use of auxiliary error pointers. To this end, the auxiliary error pointer circuits receive signal-quality-indicating signals from the data source. Such quality signals can be phase errors, amplitude errors, modulation errors, and the like. Additionally, the code converter supplies code errors indicating illegal M of N encoding or other digital modulation errors. The error syndrome generator not only generates syndromes for generating error patterns, but also generates error location signals, called code pointers, whic...