Browse Prior Art Database

Contention Resolution Between Two Processors

IP.com Disclosure Number: IPCOM000041815D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Dauby, A: AUTHOR [+2]

Abstract

In a system wherein a maintenance processor is much slower than the host processor, a contention resolution method is embodied in order to prevent the information collected by the maintenance processor from becoming obsolete before it could intervene with regard to the host CPU. The control registers placed in the host CPU and activated by both processors are controlled by the maintenance processors on a MODIFY operation based on a masking concept. As shown on Fig. 1, two processors executing different tasks communicate with each other. The information transfer in both directions is possible if each processor has a readable and a writable register respectively writable and readable by the other. These facilities are located in a bus-to-bus adapter comprising the common read/write register.

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Contention Resolution Between Two Processors

In a system wherein a maintenance processor is much slower than the host processor, a contention resolution method is embodied in order to prevent the information collected by the maintenance processor from becoming obsolete before it could intervene with regard to the host CPU. The control registers placed in the host CPU and activated by both processors are controlled by the maintenance processors on a MODIFY operation based on a masking concept. As shown on Fig. 1, two processors executing different tasks communicate with each other. The information transfer in both directions is possible if each processor has a readable and a writable register respectively writable and readable by the other. These facilities are located in a bus-to-bus adapter comprising the common read/write register. For each processor, the other one is considered to be an I/O device and has at least one address on its bus. The bus- to-bus adapter allows communication between the processors and solves the problem associated with their synchronized operations. When maintenance processor P1 is controlling and maintaining host processor P2, some control registers are located in the host processor P2 and may be accessed by both processors. Before modifying any control register in which both processors may set or reset information, P1 must know its present content. When processor P1 is much slower than processor P2, a problem is raised, because to alt...