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Logic Signal Delay Circuit

IP.com Disclosure Number: IPCOM000041825D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 60K

Publishing Venue

IBM

Related People

Murfet, PJ: AUTHOR

Abstract

The circuit shown in Fig. 1 generates from a single logic input a pair of overlapping signals with equal delays td between their respective leading and trailing edges. The circuit consists essentially of an upper current mirror combination of transistors T8 and T9 and a lower current mirror combination of transistors T5 and T6 operating between ground and -5-volt supply. The arrangement is such that the current through transistor T8 is mirrored by transistor T9 but, because of the relative values of the resistors in the emitter paths of transistors T5 and T6, the current through transistor T6 is double that through transistor T5.

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Logic Signal Delay Circuit

The circuit shown in Fig. 1 generates from a single logic input a pair of overlapping signals with equal delays td between their respective leading and trailing edges. The circuit consists essentially of an upper current mirror combination of transistors T8 and T9 and a lower current mirror combination of transistors T5 and T6 operating between ground and -5-volt supply. The arrangement is such that the current through transistor T8 is mirrored by transistor T9 but, because of the relative values of the resistors in the emitter paths of transistors T5 and T6, the current through transistor T6 is double that through transistor T5. The current values are set-up by selection of the value of resistor R1 between the collectors of transistors T8 and T5 to define a constant current I through transistor T5 and, consequently, a current 2I through transistor T6. A current of substantially I flows through transistor T8 and is mirrored by transistor T9. Diodes D1 and D2 connected to transistors T10 and T7 prevent saturation of transistors T9 and T6, respectively, during operation. An input logic signal at input terminal 1 is used to control the conductivity of transistor T11 which, in turn, switches mirror transistor T6 between its conducting and non- conducting states. A capacitor C is connected between node A and ground and is charged by current I when transistor T6 is switched off and discharged by current I when transistor T6 is switched on. Output circuits consisting of long-tail pair transistors T1, T2 and T3, T4 are connected across the diodes D1 and D2, respectively. The differential current at output terminals 2 and 3 provides one of the overlapping signals and is referred to as output 1, and the differential current at output terminals 4 and 5 provides the other overlapping signal and is referred to as output 2. I (OUTPUT 1) = (I3 - I4), where I3 and I4 are the current through transistors T3 and T4, respectively, and I (OUTPUT 2) = (I1 - I2), where I1 and I2 are the currents through transistors T1 and T2, respectively. In the steady-state condition with the input signal applied to terminal 1 at its down level, the voltage at node A is (v + 1 Vbe) above the negative supply (-5 volts), where v is the voltage across resistor R2. This voltage is applied to the base of output transistor T3 which, being 1 Vbe below the voltage on the base of transistor T4, is held in its off-state. The resultant output 1, from terminals 2 and 3, is at its down level. I (OUTPUT 1) = (0 - I4). The voltage at node A is also applied to the base of transistor T1 which is also held in its off-state by virtue of the substantially higher vol...