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Low Inductance Chip Tester Interposers

IP.com Disclosure Number: IPCOM000041827D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Bickford, HR: AUTHOR

Abstract

In the Josephson device technology, circuit chip testers must have a high density of low inductance contacts in order to provide testing of the circuit chip and to avoid the problem of differential thermal contraction which occurs when materials having different coefficients of linear expansion are used. Generally, a tester interposer is used to provide electrical contact between a space transformer and the Josephson circuit chip. Two interposers providing a high density array of low inductance contacts are shown, where one of the interposers uses cast contacts while the other uses platinum pins. Fig. 1 shows a circuit test interposer 10 having an array of miniature cast contacts 12 integrated with a silicon alignment frame 14 for chip placement.

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Low Inductance Chip Tester Interposers

In the Josephson device technology, circuit chip testers must have a high density of low inductance contacts in order to provide testing of the circuit chip and to avoid the problem of differential thermal contraction which occurs when materials having different coefficients of linear expansion are used. Generally, a tester interposer is used to provide electrical contact between a space transformer and the Josephson circuit chip. Two interposers providing a high density array of low inductance contacts are shown, where one of the interposers uses cast contacts while the other uses platinum pins. Fig. 1 shows a circuit test interposer 10 having an array of miniature cast contacts 12 integrated with a silicon alignment frame 14 for chip placement. The circuit chip 16 contains solder pads 18 while the space transformer 20 contains similar solder pads 22. Initially, a silicon substrate is sequentially and anisotropically etched to provide the following features: 1. four truncated pyramidal holes for guiding and standing pins 24, 2. partial pyramidal depression, and 3. an array of many truncated pyramids in a double row around the periphery of the depression with specified entry and exit dimensions. The array of truncated pyramids provides cavities in the silicon wafer which are used as molds for the metallic contacts 12 which are cast in these cavities. The unconstrained molten metal surfaces will give the pyramidally shaped contacts 12 as a result of surface tension. Each contact may be subsequently coated with a non-oxidizing layer, if required. The resulting tester interposer may be soldered to the space transformer 20 by a lower melting alloy than that used for the previously attached guiding and standing pins. This allows subsequent demounting for replacement or reuse. Placement of the circuit chip 16 under test is effected readily by the locating feature of the etched depression, and alignment is maintained during thermal excursion as a result of using silicon as the substrate material for the frame, space transformer, and circuit chip. Low inductance contact arrays, consisting of a set of blunt-ended platinum pins soldered to a space transformer on one end and embedded in the solder of a circuit chip on the other, can be fabricated. A demountable contact mechanism relies on the differential shrinkage of the solder with respect to the pin tip to exert a force perpendicular to the side of the pin. However, problems may be encountered due to the mechanical tolerance...