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SCR Pull-Up Circuit

IP.com Disclosure Number: IPCOM000041830D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Chan, YH: AUTHOR [+3]

Abstract

With capacitive coupling technique, it is possible to push a node above the supply voltage. However, there are two major questions to be addressed when using this technique: (1) Can the physical layout be made small enough? (2) Will the coupling always be sufficient under worst-case conditions? Fig. 1 is a known bootstrap circuit. The circuit requires three transistors to layout, and its coupling phenomenon of the B-C diode D1 is somewhat limited. To improve the coupling effect as well as to minimize layout area, the circuit configuration of Fig. 2 is disclosed. In Fig. 3A, the layout of transistors T1 and D1 of Fig. 1 is shown. Fig. 3B shows the integration of these two elements. The Fig. 3B structure results in a 24% reduction in length. However, area saving is not the only claim here.

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SCR Pull-Up Circuit

With capacitive coupling technique, it is possible to push a node above the supply voltage. However, there are two major questions to be addressed when using this technique: (1) Can the physical layout be made small enough? (2) Will the coupling always be sufficient under worst-case conditions? Fig. 1 is a known bootstrap circuit. The circuit requires three transistors to layout, and its coupling phenomenon of the B-C diode D1 is somewhat limited. To improve the coupling effect as well as to minimize layout area, the circuit configuration of Fig. 2 is disclosed. In Fig. 3A, the layout of transistors T1 and D1 of Fig. 1 is shown. Fig. 3B shows the integration of these two elements. The Fig. 3B structure results in a 24% reduction in length. However, area saving is not the only claim here. Due to the merging of the two devices, one subcollector side wall and its associated capacitance effect (Ccs) is eliminated. More importantly, the merged structure is an SCR (semiconductor-controlled rectifier). Referring to Fig. 2, when the input is high, transistor T1 and the SCR are both ON. Charge is stored in the emitter-base junction of the PNP. As with the circuit of Fig. 1, when the input goes low, transistor T1 is turned off. The collector of this transistor will accept no more current; however, the PNP is still held on by the stored charge in its base- emitter region. Because of this large B-E capacitance, node B is coupled up above the Vcc supply. W...