Browse Prior Art Database

Test Inhibit Generator

IP.com Disclosure Number: IPCOM000041834D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

Blumberg, RJ: AUTHOR [+5]

Abstract

This article describes the implementation of the CIP (Chip-e) and In-Place) and CPA (Chip Partitioning Aid, also referred to as "HALF ECIPT), inhibit controls using a single fixed wire on a semiconductor chip, and a control circuit to minimize implementation cost. The required output driver circuit states for CIP and CPA testing are as follows: (Image Omitted) System operation 1/0 1/0 Where the symbols in the table are defined as: - 1/0 - driver output circuit operates normally, the output taking the value of a logic "1" or "0" (e.g., a push-pull driver sourcing or sinking current, respectively) as determined by the circuit function (AND, etc.) and the values of its inputs; - High Z - driver output is in the "High impedance" state; i.e.

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Test Inhibit Generator

This article describes the implementation of the CIP (Chip-e) and In-Place) and CPA (Chip Partitioning Aid, also referred to as "HALF ECIPT), inhibit controls using a single fixed wire on a semiconductor chip, and a control circuit to minimize implementation cost. The required output driver circuit states for CIP and CPA testing are as follows:

(Image Omitted)

System operation 1/0 1/0 Where the symbols in the table are defined as: - 1/0 - driver output circuit operates normally, the output taking the value of a logic "1" or "0" (e.g., a push-pull driver sourcing or sinking current, respectively) as determined by the circuit function (AND, etc.) and the values of its inputs; - High Z - driver output is in the "High impedance" state; i.e., current is neither sourced nor sinked; this is done in the case of CIP testing to allow the forcing of an arbitrary logic state on the net by an external probe, and to avoid forcing unknown inputs to driven chips on multi-chip packages during CPA testing (shifting test patterns into and out of CPA shift register latches (SRLs)). The overwhelming majority of driver circuits on a chip are of the "Data" (as distinguished from the "Clock" or "Scan" types), so the authors propose the use of a common, fixed "Inhibit" wire for the Data drivers to disable those circuits for CIP and CPA testing. A separate, "globally-wired" (wired by the chip user) wire would then be used to disable (inhibit, or place the driver circuit in the "High Z" state described above) the remaining small number of "non-ECIPT" driver circuits. The use of the common Inhibit line for CPA and CIP Inhibit of Data drivers saves wiring space on the chip (and hence cost due to chip area saved), but requires that a circuit be designed with the following function: The block diagram of the circuit disclosed here which implements this function is shown in Fig. 1. Blocks 1 and 4 are off-chip receiver-type circuits for industry-standard TTL (transistor-transistor logic) interface levels, which perform the function of AND- INVERT (NAND). Resistors R1-R3 are included to insure that the inputs of the circuit will "float" to the logic "1" state unless otherwise biased by external circuitry. This is to prevent an "orthogonal" condition between driver circuits on different chips during system power on, by forcing all of the drivers to the High Z state. Blocks 2 and 3 are TTL-type internal circuits, which also perform the NAND function. The basic operation of the circuit can be explained by examining the block diagram of Fig. 1. When "-En" is at a logic "0", the...